IP Library Granted Patent US 7,053,700
Granted Patent B2
US 7,053,700 · App. 10/449,105 · Granted May 30, 2006

High-efficiency amplifier and method

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Quick Facts
Patent No.
US 7,053,700
App. No.
10/449,105
Granted
May 30, 2006
Kind
B2
Abstract

Methods and apparatus are provided for efficiently amplifying a signal. An input signal is decomposed into a plurality of two state signals, each two state signal having a respective on level and off level. This may involve sigma-delta modulation and phase splitting. Each of the two state signals is amplified with a respective switching power amplifier to produce a respective amplified signal. The amplified signals are combined to produce an amplified version of the input signal.

Claims (51)

1. A method comprising:

decomposing an input signal into a plurality of two state signals, each two state signal having a respective on level and off level;

amplifying each of the plurality of two state signals with a respective switching power amplifier to produce a respective amplified signal;

combining the amplified signals to produce an amplified version of the input signal;

wherein decomposing comprises:

processing the input signal to produce a quantized signal having N levels, where N≧3; and

performing a phase splitting function on the quantized signal to produce N−1 signals, the plurality of two state signals consisting of the N−1 signals.

2. A method according to claim 1 wherein for each two state signal, the respective on level is sufficient to saturate the respective switching power amplifier.

3. A method according to claim 2 wherein:

processing the signal to produce a quantized signal having N levels, where N≧3 comprises processing the signal with an N level Sigma-Delta modulator.

4. A method according to claim 1 wherein decomposing the input signal into the plurality of two state signals is done in a manner which substantially equalizes numbers of switching transitions between the switching power amplifiers.

5. A method according to claim 1 wherein decomposing the input signal into the plurality of two state signals is done subject to a minimum on time constraint for each switching power amplifier.

6. A method according to claim 1 wherein decomposing the input signal into the plurality of two state signals is done subject to a minimum off time constraint for each switching power amplifier.

7. A method according to claim 3 wherein decomposing the input signal into the plurality of two state signals is done subject to a minimum and/or maximum time between transitions.

8. A method according to claim 1 wherein decomposing the input signal into the plurality of two state signals is done in a manner which substantially equalizes numbers of transitions between the switching power amplifiers.

9. A method according to claim 3 wherein performing a phase splitting function on the quantized signal to produce N−1 signals, the plurality of two state signals consisting of the N−1 signals comprises:

for each quantized signal output “currentIn”, if currentIn is the same as a previously processed quantized signal output “lastIn”, making no changes to the plurality of two state signals;

if currentIn is less than lastIn, determining a set X of signals that are currently off are determined, from that set X, selecting the signals with the least number of switching events and activating the selected signals;

if currentIn is greater than lastIn, determining a set X of signals that are currently, from the set X, selecting the phases with the least number of switching events and deactivating the selected signals.

10. A method according to claim 1 wherein decomposing the input signal into the plurality of two state signals is done subject to a minimum on time constraint for each switching power amplifier.

11. A method according to claim 1 wherein decomposing the input signal into the plurality of two state signals is done subject to a minimum off time constraint for each switching power amplifier.

12. A method according to claim 1 wherein decomposing the input signal into the plurality of two state signals is done subject to a minimum and/or maximum time between transitions.

13. A method according to claim 1 further comprising:

performing a partial filtering function on each amplified signal prior to combining the amplified signals, and performing a final filtering function on the amplified version of the input signal.

14. A method according to claim 1 further comprising:

performing a filtering function on each amplified signal prior to combining the amplified signals.

15. A method according to claim 1 further comprising:

performing a final filtering function on the amplified version of the input signal.

16. A method comprising:

decomposing an input signal into a plurality of two state signals, each two state signal having a respective on level and off level;

amplifying each of the plurality of two state signals with a respective switching power amplifier to produce a respective amplified signal;

combining the amplified signals to produce an amplified version of the input signal;

applying the amplified version of the signal as a power supply signal to a power amplifier;

wherein the input signal tracks an envelope of another signal to be amplified by the power amplifier.

17. An apparatus comprising:

a signal decomposing circuit adapted to decompose an input signal into a plurality of two state signals, each two state signal having a respective on level and off level;

for each of the plurality of two states signals, a respective switching power amplifier adapted to amplify the two state signal to produce a respective amplified signal;

a combiner adapted to combine the amplified signals to produce an amplified version of the signal;

wherein the signal decomposing circuit comprises:

a modulator which produces a quantized signal having N levels, where N≧3;

a phase splitting function adapted to process the quantized signal to produce N−1 signals, the plurality of two state signals consisting of the N−1 signals.

18. An apparatus according to claim 17 wherein for each two state signal, the respective on level is sufficient to saturate the respective switching power amplifier.

19. An apparatus according to claim 17 wherein the modulator is an N level Sigma-Delta modulator.

20. An apparatus according to claim 17 wherein the signal decomposing circuit decomposes the signal into the plurality of two state signals in a manner which substantially equalize numbers of transitions between the switching power amplifiers.

21. An apparatus according to claim 17 wherein the signal decomposing circuit decomposes the signal subject to a minimum on time constraint for each switching power amplifier and/or subject to specified minimum and/or maximum time between transitions.

22. An apparatus according to claim 17 wherein the signal decomposing circuit decomposes the signal subject to a minimum off time constraint for each switching power amplifier.

23. An apparatus according to claim 17 wherein the signal decomposing circuit decomposes the signal subject to a minimum and/or maximum time between transitions.

24. An apparatus according to claim 19 wherein the phase splitting function is adapted to:

for each quantized signal output “currentIn”, if currentIn is the same as a previously processed quantized signal output “lastIn”, make no changes to the plurality of two state signals;

if currentIn is less than lastIn, determine a set X of signals that are currently off are determined, from that set X, select the signals with the least number of switching events and activate the selected signals;

if currentIn is greater than lastIn, determine a set X of signals that are currently, from the set X, select the phases with the least number of switching events and deactivate the selected signals.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2014
From: MICROSOFT CORPORATION
To: MICROSOFT TECHNOLOGY LICENSING, LLC
Reel/Frame 034541/0477 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2013
From: ROCKSTAR BIDCO, LP
To: MICROSOFT CORPORATION
Reel/Frame 029972/0256 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2011
From: NORTEL NETWORKS LIMITED
To: ROCKSTAR BIDCO, LP
Reel/Frame 027164/0356 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2003
From: SMILEY, RUSSELL; FULLER, ARTHUR
To: NORTEL NETWORKS LIMITED
Reel/Frame 014142/0846 →