A limit circuit capable of providing high gain. The limit circuit included in an FM receiver comprises, for example, seven amplifiers ( 11 to 17 ), and a BPF ( 18 ) inserted substantially in the middle thereof. Each of the amplifiers ( 11 to 17 ) operates as a differential amplifier, and has a gain of about 13 dB. The BPF ( 18 ) serving as a limit circuit passes components in a bandwidth wider than the bandwidth of the signal to be amplified. The level of 1/f noise and heat noise can be reduced by eliminating low-frequency components and high-frequency components of the Signal amplified by the four amplifiers ( 11 to 14 ), respectively. Therefore, each of the amplifiers ( 15 to 17 ) connected to the rear end of the BPF ( 18 ) is not animated by the noise component.
1. A limit circuit provided in a foregoing stage to a detection circuit of a receiver, comprising:
amplifiers cascaded in a plurality of stages,
wherein said amplifier in each stage has high-frequency component elimination unit for eliminating components higher-frequency than an upper limit of a band of a signal inputted to said detection circuit and low-frequency component elimination unit for eliminating the components lower-frequency than a lower limit of the band of the signal; and said low frequency component elimination unit comprising a feedback circuit for feeding back the component lower-frequency than a lower limit of the band of said detected signal included in the output signal of said amplifier in each stage to said amplifier in each stage in a reverse phase.
2. The limit circuit according to claim 1 , wherein said low-frequency component elimination unit is a high-pass filter in which a cutoff frequency is set at a value lower than said lower limit.
3. The limit circuit according to claim 1 , wherein said amplifiers are differential amplifiers for differentially operating two transistors, and said low-frequency component elimination unit is a feedback circuit for inputting in phase to said two transistors a signal of low-frequency components of differential output signals of said amplifier in each stage.
4. The limit circuit according to claim 1 , wherein said high-frequency component elimination unit is a low-pass filter in which a cutoff frequency is set at a value higher than said upper limit.
5. The limit circuit according to claim 4 , wherein a parasitic capacitance of a transistor included in said amplifier in the next stage is used as a capacitor included in said low-pass filter.
6. The limit circuit according to claim 1 , wherein said limit circuit is integrally formed on a semiconductor substrate by using a CMOS process or a MOS process.
7. The limit circuit according to claim 1 , wherein p-channel type FETs are used as amplifying elements included in said amplifiers.
8. The limit circuit according to claim 1 , wherein p-channel type FETs are used as amplifying elements included in said amplifiers in first to m-th stages at least, and n-channel type FETs are used as the amplifying elements included in said amplifiers from an m+1-th stage onward.
9. The limit circuit according to claim 6 , wherein said semiconductor substrate has an N-well formed thereon and all or a part of said component parts are formed on the N-well.
10. The limit circuit according to claim 9 , wherein said semiconductor substrate has a guard ring formed around said component parts.
11. The limit circuit according to claim 10 , wherein said guard ring is formed from said semiconductor substrate's surface down to a position deeper than said N-well.
12. A limit circuit provided in a foregoing stage to a detection circuit of a receiver, comprising:
amplifiers cascaded in a plurality of stages,
wherein said amplifier in each stage has high-frequency component elimination unit for eliminating components higher-frequency than an upper limit of a band of a detected signal inputted to said detection circuit; and
a feedback circuit for feeding back the components lower-frequency than a lower limit of the band of said detected signal included in the output signal of said amplifier in the final stage to said amplifier in a first stage in a reversed phase.
13. The limit circuit according to claim 12 , wherein said high-frequency component elimination unit is a low-pass filter in which a cutoff frequency is set at a value higher than said upper limit.
14. The limit circuit according to claim 13 , wherein a parasitic capacitance of a transistor included in said amplifier in the next stage is used as a capacitor included in said low-pass filter.
15. The limit circuit according to claim 12 , wherein said limit circuit is integrally formed on a semiconductor substrate by using a CMOS process or a MOS process.
16. The limit circuit according to claim 12 , wherein p-channel type FETs are used as amplifying elements included in said amplifiers.
17. The limit circuit according to claim 12 , wherein p-channel type FETs are used as amplifying elements included in said amplifiers in first to m-th stages at least, and n-channel type FETs are used as the amplifying elements included in said amplifiers from an m+1-th stage onward.
18. The limit circuit according to claim 15 , wherein said semiconductor substrate has an N-well formed thereon and all or a part of said component parts are formed on the N-well.
19. The limit circuit according to claim 18 , wherein said semiconductor substrate has a guard ring formed around said component parts.
20. The limit circuit according to claim 19 , wherein said guard ring is formed from said semiconductor substrate's surface down to a position deeper than said N-well.