Multithreaded processor with multiple caches
A multithreaded processor includes multiple level-1 program caches and multiple level-1 data caches to decrease the likelihood of cache misses after thread switches. By using multiple level-1 caches, execution of a first thread does not cause instructions or data cached for a second thread to be replaced. Thus, when the second thread is being executed the occurrence of cache misses is reduced.
1. A cache system for a multithreaded processor having a single processing core and a plurality of active threads, the cache system comprising:
a first thread micro-cache directly coupled to the single processing core; and
a second thread micro-cache directly coupled to the single processing core,
wherein the first thread micro-cache is assigned a first active thread and the second thread micro-cache is assigned a second active thread.
2. The cache system of claim 1 , further comprising a level-2 cache coupled to the first thread micro-cache and the second thread micro-cache.
3. The cache system of claim 1 , further comprising a global micro-cache.
4. The cache system of claim 1 , wherein the first thread micro-cache and the second thread micro-cache are thread data micro-caches.
5. The cache system of claim 1 , wherein the first thread micro-cache and the second thread micro-cache are thread program micro-caches.
6. The cache system of claim 5 , further comprising:
a first thread data micro-cache coupled to the single processing core; and
a second thread data micro-cache coupled to the single processing core.
7. The cache system of claim 6 , wherein the first thread data micro-cache and the first thread program micro-cache share a thread tag and a status flag.
8. The cache system of claim 6 , further comprising:
a global data micro-cache coupled to the single processing core; and
a global program micro-cache coupled to the single processing core.
9. The cache system of claim 1 , further comprising a third thread micro-cache directly coupled to the single processing core, wherein the third thread micro-cache is assigned a third active thread.
10. The cache system of claim 1 , wherein the first thread micro-cache is assigned a third active thread.
11. The cache system of claim 1 , wherein the first thread micro-cache comprises a thread tag for storing a rigid thread tag.
12. The cache system of claim 1 , wherein the first thread micro-cache comprises a status flag.