Apparatus and method for monitoring and predicting failures in system interconnect

1. A method for detecting high impedance failures in a system interconnect, comprising steps of:

(a) measuring resistance of a connection of one or more representative sets of pins on a partitioned chip to a circuit board, wherein the measuring step is executed while the circuit board is operating, and wherein the measuring step comprises:

partitioning the chip into a plurality of pin areas; and

selecting the one or more representative sets of pins from pins within each pin area; and

(b) determining if the measured resistance of each of the one or more representative sets of pins is less than a threshold value.

2. The method of claim 1 , wherein step (b) determine that the measured resistance of each of the one or more representative sets of pins is less than the threshold value, the method further comprising:

determining if the measured resistance of each of the one or more representative sets of pins is within a certain percentage of one another.

3. The method of claim 2 , wherein the measure resistance of each of the one or more representative pins is not within the certain percentage of one another, the method further comprising:

issuing a warning that the measured resistances do not match.

4. The method of claim 2 , wherein the certain percentage is ten percent.

5. The method of claim 1 , wherein step (b) determines that the measured resistance of any of the one or more representative sets of pins exceeds the threshold value, the method further comprising:

determining if the exceeding measured resistance value(s) is less than a maximum allowable resistance value.

6. A method for detecting high impedance failures in a system interconnect, comprising steps of:

(a) measuring resistance of a connection of one or more representative sets of pins on a partitioned chip to a circuit board, wherein the measuring step is executed while the circuit board is operating;

(b) determining if the measured resistance of each of the one or more representative sets of pins is less than a threshold value, wherein the determining step determines that the measured resistance of any of the one or more representative sets of pins exceeds the threshold value;

(c) determining if the exceeding measured resistance value(s) is less than a maximum allowable resistance value.

(d) if the exceeding measured resistance value(s) is less than the maximum allowable resistance value, repeating step (a) a number of iterations each separated by an interval of time; and

(e) determining if the measured resistance values from the repeating step are consistent with one another.

7. The method of claim 6 , wherein the measured resistance values from the repeating step are consistent with one another, the method further comprising:

issuing a severe warning indicating that an interconnect failure may occur soon.

8. The method of claim 6 , wherein the measured resistance values from the repeating step are inconsistent with one another, the method further comprising:

issuing a warning of inconsistency.

9. A method for detecting high impedance failures in a system interconnect, comprising steps of:

(a) measuring resistance of a connection of one or more representative sets of pins on a partitioned chip to a circuit board, wherein the measuring step is executed while the circuit board is operating;

(b) determining if the measured resistance of each of the one or more representative sets of pins is less than a threshold value, wherein the determining step determines that the measured resistance of any of the one or more representative sets of pins exceeds the threshold value;

(c) determining if the exceeding measured resistance value(s) is less than a maximum allowable resistance value.

(d) if any of the exceeding measured resistance value(s) is more than the maximum allowable resistance value, repeating step (a) a number of iterations each separated by an interval of time; and

(e) determining if the measure resistance values from the repeating step are consistent with one another.

10. The method of claim 9 , wherein the measured resistance values from the repeating step are consistent with one another, the method further comprising:

issuing a critical warning indicating that an interconnect failure is imminent.

11. The method of claim 9 , wherein the measured resistance values from the repeating step are inconsistent with one another, the method further comprising:

issuing a warning of inconsistency.

12. The method of claim 1 , further comprising steps of:

waiting an interval; and

repeating step (a) and step (b).

13. The method of claim 1 , further comprising steps of:

communicating the measured resistance data to a system management device; and

storing the measured resistance data for each representative set of pins.

14. A method for detecting high impedance failures in a system interconnect, comprising steps of:

(a) measuring resistance of a connection of one or more representative sets of pins on a partitioned chip to a circuit board, wherein the measuring step is executed while the circuit board is operating;

(b) determining if the measured resistance of each of the one or more representative sets of pins is less than a threshold value;

(c) determining a good resistance value (x); and

(d) determining a maximum allowable resistance value (y);

wherein the threshold value is a sum of the good resistance value and half of the maximum allowable resistance value minus the good resistance value (x+(y−x)/2).

15. The method of claim 1 , further comprising steps of:

partitioning an application specific integrated circuit (ASIC) into pin areas; and

routing a signal path from each of the one or more representative sets of pins to a resistance continuity monitoring circuit (RCMC).

16. The method of claim 1 , further comprising a step of:

determining if the measured resistances of the one or more representative sets of pins fits a Gaussian distribution.

17. A computer-readable medium comprising instructions for:

(a) measuring resistance of a connection of one or more representative sets of pins on a partitioned chip to a circuit board, wherein the measuring step is executed while the circuit board is operating, and wherein the measuring step comprises:

partitioning the chip into a plurality of pin areas: and

selecting the one or more representative sets of pins from pins within each pin area; and

(b) determining if the measured resistance of each of the one or more representative sets of pins is less than a threshold value.

18. The computer-readable medium of claim 17 further comprising instructions for:

determining if the measured resistance of each of the one or more representative sets of pins is within a certain percentage of one another.

19. The computer-readable medium of claim 17 further comprising instructions for:

determining if an exceeding measured resistance value(s) is less than a maximum allowable resistance value.

20. A computer-readable medium comprising instructions for:

(a) measuring resistance of a connection of one or more representative sets of pins on a partitioned chip to a circuit board, wherein the measuring step is executed while the circuit board is operating;

(b) determining if the measured resistance of each of the one or more representative sets of pins is less than a threshold value;

(c) repeating step (a) a number of iterations each separated by an interval of time; and

(d) determining if the measured resistance values from the repeating step are consistent with one another.

21. The computer-readable medium of claim 17 further comprising instructions for:

waiting an interval; and

looping back to step (a).