Granted Patent B2

US 7,317,725 · App. 10/453,878 · Granted Jan 8, 2008

Abstract

Claims (38)

1. A DS0 time switch for cross connecting predefined input and output DS0 pairs for creating a data path in a communication network, said time switch comprising:

(a) an input buffer for receiving input cells;

(b) a reassembly state machine for retrieving first information from said input cells in accordance with cross-connect control requirements;

(c) a frame buffer for storing said first information retrieved by said reassembly state machine in one or more first selected bins of a plurality of bins in accordance with at one or more first associated input DS0s; and

(d) a segmentation state machine for retrieving second information from one or more second selected bins of said plurality of bins in said frame buffer in accordance with one or more second associated output DS0s and using said second information for assembling an output cell and transmitting said one or more second associated output DS0s via said output cell.

2. A time switch as defined in claim 1 , wherein said first information includes data.

3. A time switch as defined in claim 2 , wherein said first information further includes signalling.

4. A time switch as defined in claim 1 further including a segmentation timer for synchronizing the transmission of said output cell after assembly.

5. A time switch as defined in claim 1 , wherein said input buffer receives data from a remote terminal and said output cell is transmitted to a host terminal.

6. A time switch as defined in claim 1 , wherein said input buffer receives data from a host terminal and said output cell is transmitted to a remote terminal.

7. A time switch as defined in claim 1 instantiated within a line interface card on a remote terminal.

8. A time switch as defined in claim 1 instantiated within an Asynchronous Transfer Mode (ATM) switch on a remote terminal.

9. A time switch as defined in claim 1 instantiated within a Time Division Multiplexed (TDM) card on a remote terminal.

10. A time switch as defined in claim 1 instantiated within a server card on a remote terminal.

11. A time switch as defined in claim 1 instantiated within an Asynchronous Transfer Mode (ATM) switch on a host terminal.

12. A time switch as defined in claim 1 instantiated within a Time Division Multiplexed (TDM) card on a host terminal.

13. A time switch as defined in claim 1 instantiated within a server card on a host terminal.

14. A time switch as defined in claim 1 , wherein said input cell is an ATM cell in a first format and said output cell is an ATM cell in a second format.

15. A time switch as defined in claim 14 , wherein first format is the same as said second format.

16. A time switch as defined in claim 14 , wherein said first and second formats are selected from the group including TDM interfaces, custom formatted AAL type 0 , AAL type 1 , AAL type 2 AAL type 5 , IP, and Ethernet.

17. A time switch as defined in claim 14 , wherein a format is used for transferring cells between a TDM interface and said time switch such that data is transmitted as soon as it is available, thereby reducing time delay of said data.

18. A time switch as defined in claim 17 , wherein said format comprises a 24-DS0 frame and associated signalling.

19. A time switch as defined in claim 18 , wherein each cell comprises two frames of data and a cell is transmitted after every two frames.

20. A time switch as defined in claim 19 , wherein said signalling is transported in a cell with a same virtual circuit (VC) as said data, but is differentiated by a bit in a header of said cell.

21. A time switch as defined in claim 19 , further including a pair of virtual circuits (VCs), wherein one of said VCs is used for delivering data and the other of said VCs is used for delivering signalling.

22. A time switch as defined in claim 18 , wherein each cell comprises a single frame of data and a cell is transmitted after every frame.

23. A time switch as defined in claim 22 , wherein said signalling is included in unused bytes of said cell.

24. A time switch as defined in claim 17 , wherein said format comprises a 48-DS0 frame and associated signalling and each cell including a single frame of data is transmitted after every frame.

25. A time switch as defined in claim 24 , wherein said signalling is transported in a cell with a same virtual circuit (VC) as said data, but is differentiated by a bit in a header of said cell.

26. A time switch as defined in claim 24 , further including a pair of virtual circuits (VCs), wherein one of said VCs is used for delivering data and the other of said VCs is used for delivering signalling.

27. A time switch as defined in claim 17 , wherein said format comprises a DS0 frame and associated signalling and a payload of each cell includes at least one frame and an AAL type 1 SAR-PDU header byte.

28. A time switch as defined in claim 17 , wherein said format comprises a full DS1 and associated framing bit per frame, plus extra DS0s to fill the ATM cell.

29. A time switch as defined in claim 28 , wherein said framing bit is transported in a payload of said cell.

30. A time switch as defined in claim 28 , wherein said framing bit is transported in a header of said cell.

31. A time switch as defined in claim 1 , wherein said time switch enables use of a common backplane for transport of a plurality of different data formats.

32. A time switch as defined in claim 1 , further comprising TDM interfaces for cross connecting both TDM and ATM data.

33. A networked system comprising a host terminal and a remote terminal including a time switch as defined in claim 1 for providing DS0 cross-connect capability with packet-based transport of DS0s among a plurality of interconnected TDM interfaces and common cross-connect devices.

34. A standalone system comprising a time switch as defined in claim 1 for providing DS0 cross-connect capability with packet-based transport of DS0s among a plurality of interconnected TDM interfaces and common cross-connect devices.

Assignments (9)