Array substrate for liquid crystal display device
View Patent ↗The present invention is related to an array substrate for use in a liquid crystal display. The array substrate includes a transparent substrate; a plurality of gate lines arranged over the transparent substrate in a transverse direction; a plurality of data lines arranged over the transparent substrate in a longitudinal direction substantially perpendicular to the plurality of gate lines, intersections of the plurality of data lines and the plurality of gate lines defining a plurality of pixel regions; a gate driver contacting ends of the plurality of gate lines and sequentially scanning a gate pulse to the plurality of gate lines; a data driver contacting ends of the plurality of data lines and applying a data pulse to the plurality of data lines; a plurality of pixel electrodes disposed in the plurality of pixel regions; a plurality of first thin-film transistors disposed in the plurality of pixel regions, each first thin-film transistor including a gate electrode connected to a gate line, a source electrode connected to a data line, and a drain electrode connected to the pixel region; a feed line outputting an OFF voltage to the plurality of first thin-film transistors; and a plurality of second thin-film transistors contacting each other and connecting the feed line to the plurality of gate lines.
1. An array substrate for use in a liquid crystal display, comprising:
a transparent substrate;
a plurality of gate lines arranged over the transparent substrate in a transverse direction;
a plurality of data lines arranged over the transparent substrate in a longitudinal direction substantially perpendicular to the plurality of gate lines, intersections of the plurality of data lines and the plurality of gate lines defining a plurality of pixel regions;
a gate driver contacting ends of the plurality of gate lines and sequentially scanning a gate pulse to the plurality of gate lines;
a data driver contacting ends of the plurality of data lines and applying a data pulse to the plurality of data lines;
a plurality of pixel electrodes disposed in the plurality of pixel regions;
a plurality of first thin-film transistors disposed in the plurality of pixel regions, each first thin-film transistor including a gate electrode connected to a gate line, a source electrode connected to a data line, and a drain electrode connected to the pixel region;
a feed line outputting an OFF voltage to the plurality of first thin-film transistors; and
a plurality of second thin-film transistors contacting each other and connecting the feed line to the plurality of gate lines.
2. The array substrate of claim 1 , wherein each of the plurality of second thin-film transistors receives the gate pulse from a first gate line and delivers the OFF voltage from the feed line to a second gate line.
3. The array substrate of claim 1 , wherein each second thin-film transistor includes a drain electrode connected to a first gate line, a source electrode connected to the feed line, and a gate electrode connected to a second gate line.
4. The array substrate of claim 1 , wherein the data driver, the gate driver, the plurality of second thin-film transistors, and the feed line are formed over the transparent substrate.
5. The array substrate of claim 1 , wherein the OFF voltage output from the feed line is a ground voltage.
6. The array substrate of claim 1 , wherein the OFF voltage output from the feed line is a common voltage.
7. The array substrate of claim 1 , wherein the gate pulse applied from the gate driver to the plurality of gate lines includes a gate high voltage, which is an ON voltage turning on the plurality of first thin-film transistors, and a gate low voltage, which is an OFF voltage turning off the plurality of first thin-film transistors.
8. The array substrate of claim 7 , wherein the OFF voltage output from the feed line is the gate low voltage of the gate pulse.
9. The array substrate of claim 1 , wherein the OFF voltage shortens a falling time of the gate pulse.
10. The array substrate of claim 1 , wherein the OFF voltage is applied to the first thin-film transistors through the plurality of second thin-film transistors and gate lines.
11. The array substrate of claim 10 , wherein a falling time of the gate pulse is similar in each of the plurality of first thin-film transistors.
12. The array substrate of claim 1 , wherein each of the plurality of second thin-film transistors delivers the OFF voltage from the feed line to a first gate line using the gate pulse from an adjacent gate line.
13. The array substrate of claim 1 , wherein the feed line is disposed in a periphery of the array substrate opposing the gate driver.
14. An array substrate for use in a liquid crystal display, comprising:
a transparent substrate;
a plurality of gate lines arranged over the transparent substrate in a transverse direction;
a plurality of data lines arranged over the transparent substrate in a longitudinal direction substantially perpendicular to the plurality of gate lines, intersections of the plurality of data lines and the plurality of gate lines defining a plurality of pixel regions;
a gate driver contacting ends of the plurality of gate lines and sequentially scanning a gate pulse to the plurality of gate lines;
a data driver contacting ends of the plurality of data lines and applying a data pulse to the plurality of data lines;
a plurality of first thin-film transistors disposed in the plurality of pixel regions;
a feed line outputting an OFF voltage to the plurality of first thin-film transistors; and
a plurality of second thin-film transistors connecting the feed line to the plurality of gate lines.
15. The array substrate of claim 14 , wherein each of the plurality of second thin-film transistors receives the gate pulse from a first gate line and delivers the OFF voltage from the feed line to a second gate line.
16. The array substrate of claim 14 , wherein each first thin-film transistor includes a drain electrode connected to the pixel region, a source electrode connected to a data line, and a gate electrode connected to a gate line.
17. The array substrate of claim 14 , wherein each second thin-film transistor includes a drain electrode connected to a first gate line, a source electrode connected to the feed line, and a gate electrode connected to a second gate line.
18. The array substrate of claim 14 , wherein the data driver, the gate driver, the plurality of second thin-film transistors, and the feed line are formed over the transparent substrate.
19. The array substrate of claim 14 , wherein the OFF voltage output from the feed line is a ground voltage.
20. The array substrate of claim 14 , wherein the OFF voltage output from the feed line is a common voltage.
21. The array substrate of claim 14 , wherein the gate pulse applied from the gate driver to the plurality of gate lines includes a gate high voltage, which is an ON voltage turning on the plurality of first thin-film transistors, and a gate low voltage, which is an OFF voltage turning off the plurality of first thin-film transistors.
22. The array substrate of claim 21 , wherein the OFF voltage output from the feed line is the gate low voltage of the gate pulse.
23. The array substrate of claim 14 , wherein the OFF voltage shortens a falling time of the gate pulse.
24. The array substrate of claim 14 , wherein the OFF voltage is applied to the first thin-film transistors through the plurality of second thin-film transistors and gate lines.
25. The array substrate of claim 24 , wherein a falling time of the gate pulse is similar in each of the plurality of first thin-film transistors.
26. The array substrate of claim 14 , wherein each of the plurality of second thin-film transistors delivers the OFF voltage from the feed line to a first gate line using the gate pulse from an adjacent gate line.
27. The array substrate of claim 14 , wherein the feed line is disposed in a periphery of the array substrate opposing the gate driver.