Method and apparatus for grouping flip-flops by timing
View Patent ↗One embodiment of the present invention provides a system that facilitates placing flip-flops in an integrated circuit based on timing requirements. The system operates by first receiving a netlist for flip-flop connectivity. Next, the system determines a metal layer class definition for each signal in the netlist based upon timing requirements of a corresponding flip-flop. The system then classifies a flip-flop instance using the metal layer class definition by defining a flip-flop type for each flip-flop instance and associating the flip-flop with a group of other flip-flops that have a same metal layer class definition. Finally, determining a position for the group by replacing an existing repeater in the integrated circuit with the group of flip-flops.
1. A method for placing flip-flops in an integrated circuit based upon timing, comprising:
receiving a netlist specifying flip-flop connectivity, wherein receiving the netlist includes receiving a hierarchical block placement for blocks on the integrated circuit, and wherein the hierarchical block placement includes a repeater placement in a channel area of the integrated circuit;
determining a metal layer class definition for a flip-flop in the netlist based upon timing requirements of the flip-flop;
classifying a flip-flop instance using the metal layer class definition;
defining a flip-flop type for each flip-flop instance;
associating the flip-flop with a group of other flip-flops that have a same metal layer class definition;
searching for available flip-flop positions based on the repeater placement; and
determining a position for the group of flip-flops by replacing an existing repeater in the integrated circuit with the group of flip-flops.
2. The method of claim 1 , further comprising:
extracting resistor-capacitor (RC) parasitic data for each I/O pin of each block on the integrated circuit; and
using the RC parasitic data to determine signal timing at each I/O pin.
3. The method of claim 2 , further comprising calculating a wire delay for each I/O signal line used for interconnecting blocks on the integrated circuit.
4. The method of claim 3 , wherein calculating the wire delay for each I/O signal line involves using a wire parasitic equation.
5. A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for placing flip-flops in an integrated circuit based upon timing, comprising:
receiving a netlist specifying flip-flop connectivity, wherein receiving the netlist includes receiving a hierarchical block placement for blocks on the intearated circuit, and wherein the hierarchical block placement includes a repeater placement in a channel area of the integrated circuit;
determining a metal layer class definition for a flip-flop in the netlist based upon timing requirements of the flip-flop;
classifying a flip-flop instance using the metal layer class definition;
defining a flip-flop type for each flip-flop instance;
associating the flip-flop with a group of other flip-flops that have a same metal layer class definition;
searching for available flip-flop positions based on the repeater placement; and
determining a position for the group of flip-flops by replacing an existing repeater in the integrated circuit with the group of flip-flops.
6. The computer-readable storage medium of claim 5 , the method further comprising:
extracting resistor-capacitor (RC) parasitic data for each I/O pin of each block on the integrated circuit; and
using the RC parasitic data to determine signal timing at each I/O pin.
7. The computer-readable storage medium of claim 6 , the method further comprising calculating a wire delay for each I/O signal line used for interconnecting blocks on the integrated circuit.
8. The computer-readable storage medium of claim 7 , wherein calculating the wire delay for each I/O signal line involves using a wire parasitic equation.
9. An apparatus for placing flip-flops in an integrated circuit based upon timing, comprising:
a receiving mechanism configured to receive a netlist specifying flip-flop connectivity, wherein receiving the netlist includes receiving a hierarchical block placement for blocks on the integrated circuit, and wherein the hierarchical block placement includes a repeater placement in a channel area of the integrated circuit;
a determining mechanism configured to determine a metal layer class definition for a flip-flop in the netlist based upon timing requirements of the flip-flop;
a classifying mechanism configured to classify a flip-flop instance using the metal layer class definition;
a defining mechanism configured to define a flip-flop type for each flip-flop instance;
an associating mechanism configured to associate the flip-flop with a group of other flip-flops that have a same metal layer class definition;
a searching mechanism configured to search for available flip-flop positions based on the repeater placement; and
a position determining mechanism configured to determine a position for the group of flip-flops by replacing an existing repeater in the integrated circuit with the group of flip-flops.
10. The apparatus of claim 9 , further comprising:
a extracting mechanism configured to extract resistor-capacitor (RC) parasitic data for each I/O pin of each block on the integrated circuit; and
a data using mechanism configured to use the RC parasitic data to determine signal timing at each I/O pin.
11. The apparatus of claim 10 , further comprising a calculating mechanism configured to calculate a wire delay for each I/O signal line used for interconnecting blocks on the integrated circuit.
12. The apparatus of claim 11 , wherein calculating the wire delay for each I/O signal line involves using a wire parasitic equation.