Communication network and method of communicating data on the same

1. A network comprising:

a first module comprising a master communication interface; and

a second module comprising

a slave communication interface in communication with the master communication interface, the slave communication interface including

(n) input terminals adapted to receive a (n)-bit input, wherein (n) represents an integer greater than one,

(n) output terminals adapted to communicate a (n)-bit output, and

(m) control terminals, and

a processor and memory electrically connected to the (n) input, (n) output, and (m) control terminals, the memory being configurable to include 2 (m) block, each block consisting of 2 (n) sub-blocks, each sub-block consisting of (n) bits.

2. A network as set forth in claim 1 wherein (n) is equal to four and (in) is equal to two.

3. A network as set forth in claim 2 wherein the slave communication interface further includes an (m+1) control terminal electrically connected to the processor and memory.

4. A network as set forth in claim 1 wherein the network further comprises a bus, and wherein the master and slave communication interfaces communicate via the bus.

5. A network as set forth in claim 4 wherein the bus consists of up to (n) wires.

6. A network as set forth in claim 4 wherein the bus consists of two wires.

7. A network as set forth in claim 4 wherein the first module further includes a low-voltage power source, and wherein the bus also transmits low-voltage power to the slave communication interface.

8. A network as set forth in claim 4 wherein the bus is an AS-Interface cable, and wherein the master and slave communication interfaces are compatible with the AS-Interface cable.

9. A network as set forth in claim 1 wherein the processor is selected from the group consisting of a microprocessor, a PLC, a microcontroller, and an ASIC.

10. A network comprising:

an AS-Interface compatible master communication interface;

an AS-Interface cable; and

a module comprising

an AS-Interface compatible slave communication interface in communication with the AS-Interface master via the AS-Interface cable, the AS-Interface slave including

four input terminals adapted to receive a four-bit input;

four output terminals adapted to communicate a four-bit output;

two control terminals adapted to communicate a two-bit control, and

a microprocessor and memory electrically connected to the input, output, and control terminals, the memory being configurable to include four blocks, each block consisting of 16 sub-blocks, and each sub-block consisting of four bits.

11. A method of communicating data over a network, the network comprising

a first module comprising a master communication interface, and

a second module comprising

a slave communication interface in communication with the master communication interface, the slave communication interface including one or more terminals adapted to communicate (n)-bit messages, where (n) is an integer greater than one, and

a processor and memory electrically connected to the terminals, the memory being configurable to include a block consisting of 2 (n) sub-blocks, each sub-block having (n) bits, the method comprising the acts of:

communicating a first (n)-bit message from the master communication interface to the slave communication interface;

communicating the first (n)-bit message from the slave communication interface to the processor;

at the processor and memory,

identifying one of the sub-blocks with the first (n)-bit message;

obtaining the identified sub-block;

communicating a second (n)-bit message including the obtained data from the processor to the slave communication interface; and

communicating the second (n)-bit message from the slave communication interface to the master communication interface.

12. A method as set forth in claim 11 wherein the one or more terminals include (n)-input terminals adapted to receive an (n)-bit message and (n)-output terminals adapted to output an (n)-bit message, wherein the act of communicating a first (n)-bit message from the slave communication interface to the processor includes the act of communicating the first (n)-bit message via the (n)-output terminals, and wherein the act of communicating the second (n)-bit message from the processor to the slave communication interface includes the act of communicating the second (n)-bit message via the (n)-input terminals.

13. A method as set forth in claim 12 wherein the network further comprises a first (n) channels connecting the (n)-input terminals to the processor and a second (n) channels connecting the (n)-output terminals to the processor, wherein the act of communicating the first (n)-bit message via the (n)-output terminals includes communicating each bit of the first (n)-bit message on a respective channel of the first (n) channels, and wherein the act of communicating the second (n)-bit message via the (n)-input terminals includes communicating each bit of the second (n)-bit message on a respective channel of the second (n) channels.

14. A method as set forth in claim 11 wherein each sub-block is identified binaryly from (0) to (n−1), and wherein the act of identifying one of the sub-blocks includes identifying the sub-block corresponding to the first (n)-bit message.

15. A method as set forth in claim 11 wherein the network further comprises a two-wire bus, wherein the master and slave communication interfaces communicate via the bus, wherein the act of communicating a first (n)-bit message from the master communication interface to the slave communication interface includes the act of sequentially communicating the (n)-bits of the first (n)-bit message from the master communication interface to the slave communication interface, and wherein the act of communicating the second (n)-bit message from the slave communication interface to the master communication interface includes the act of sequentially communicating the (n)-bits of the second (n)-bit message from the slave communication interface to the master communication interface.

16. A method as set forth in claim 11 wherein the one or more terminals are further adapted to communicate (m)-bit messages, where (in) is an integer greater than one, and wherein the memory is configurable to include 2 (m) blocks, each block consisting of 2 (n) sub-blocks, each sub-block consisting of (n) bits, and wherein the method further comprises the acts of:

communicating an (m)-bit message from the master communication interface to the slave communication interface;

communicating an (m)-bit message from the slave communication interface to the processor;

at the processor and memory,

identifying one of the blocks with the (m)-bit message; and

wherein the act of identifying one of the sub-blocks is performed on the identified block.

17. A method as set forth in claim 16 wherein (n) is equal to four and (m) is equal to two.

18. A method as set forth in claim 11 and further comprising the acts of:

communicating a third (n)-bit message from the master communication interface to the slave communication interface;

communicating the third (n)-bit message from the slave communication interface to the processor;

at the processor and memory,

identifying a second sub-block with the third (n)-bit message;

obtaining the second identified sub-block;

communicating a fourth (n)-bit message including the obtained data of the second identified sub-block from the processor to the slave communication interface;

communicating the fourth (n)-bit message from the slave communication interface to the master communication interface;

at the master communication interface,

storing at least a portion of the second (n)-bit message; and

combining the stored portion of the second (n)-bit message with at least a portion of the fourth (n)-bit message.

19. A method of communicating data over a network, the network comprising

a first module comprising a master communication interface, and

a second module comprising

a slave communication interface in communication with the master communication interface, the slave communication interface including one or more terminals adapted to communicate (n)-bit messages, where (n) is an integer greater than one, and

a processor and memory electrically connected to the terminals, the memory being configurable to include a block consisting of 2 (n) sub-blocks, each sub-block having (n) bits, the method comprising the acts of:

communicating a first (n)-bit message from the master communication interface to the slave communication interface;

communicating the first (n)-bit message from the slave communication interface to the processor;

communicating a second (n)-bit message from the master communication interface to the slave communication interface;

communicating the second (n)-bit message from the slave communication interface to the processor;

at the processor and memory,

identifying one of the sub-blocks with the first (n)-bit message; and

writing the second (n)-bit message in the identified sub-block.

20. A method as set forth in claim 19 wherein the one or more terminals include (n)-output terminals adapted to output an (n)-bit message, wherein the act of communicating a first (n)-bit message from the slave communication interface to the processor includes the act of communicating the first (n)-bit message via the (n)-output terminals, and wherein the act of communicating the second (n)-bit message from the slave communication interface to the processor includes the act of communicating the second (n)-bit message via the (n)-output terminals.

21. A method as set forth in claim 20 wherein the network further comprises (n) channels connecting the (n)-output terminals to the processor, wherein the act of communicating the first (n)-bit message via the (n)-output terminals includes communicating each bit of the first (n)-bit message on a respective channel of the (n) channels, and wherein the act of communicating the second (n)-bit message via the (n)-output terminals includes communicating each bit of the second (n)-bit message on a respective channel of the (n) channels.

22. A method as set forth in claim 19 wherein each sub-block is identified binaryly from (0) to (n−1), and wherein the act of identifying one of the sub-blocks includes identifying the sub-block corresponding to the first (n)-bit message.

23. A method as set forth in claim 19 wherein the network further comprises a two-wire bus, wherein the master communication interface and slave communication interface communicate via the bus, wherein the act of communicating a first (n)-bit message from the master communication interface to the slave communication interface includes the act of sequentially communicating the (n)-bits of the first (n)-bit message from the master communication interface to the slave communication interface, and wherein the act of communicating the second (n)-bit message from the master communication interface to the slave communication interface includes the act of sequentially communicating the (n)-bits of the second (n)-bit message from the master communication interface to the slave communication interface.

24. A method as set forth in claim 19 wherein the one or more terminals are further adapted to communicate (m)-bit messages, where (in) is an integer greater than one, and wherein the memory is configurable to include 2 (m) blocks, each block consisting of 2 (n) sub-blocks, each sub-block consisting of (n) bits, and wherein the method further comprises the acts of:

communicating an (m)-bit message from the master communication interface to the slave communication interface;

communicating an (m)-bit message from the slave communication interface to the processor;

at the processor and memory,

identifying one of the blocks with the (m)-bit message; and

wherein the act of identifying one of the sub-blocks is performed on the identified block.

25. A method as set forth in claim 24 wherein (n) is equal to four and (m) is equal to two.

26. A method as set forth in claim 19 and further comprising the acts of:

providing a (p)-bit message, where (p) is an integer greater than (n);

decomposing the (p)-bit message to result in the second (n)-bit message and a fourth (n)-bit message, at least part of the second (n)-bit message being a portion of the (p)-bit message and at least part of the fourth (n)-bit message being a portion of the (p)-bit message;

communicating a third (n)-bit message from the master communication interface to the slave communication interface;

communicating the third (n)-bit message from the slave communication interface to the processor;

communicating the fourth (n)-bit message from the master communication interface to the slave communication interface;

communicating the fourth (n)-bit message from the slave communication interface to the processor;

at the processor and memory,

identifying a second sub-block with the third (n)-bit message; and

writing the fourth (n)-bit message in the identified second sub-block.

27. A method of communicating data over a network, the network comprising

a first module comprising a master communication interface, and

a bus electrically connected to the master communication interface,

a second module comprising

a slave communication interface electrically connected to the bus, the slave communication interface including (n) input terminals adapted to received a (n)-bit input, n-output terminals adapted to output a (n)-bit output, (m) control terminals adapted to communicate an (m)-bit control, and an W/R terminal adapted to communicate an W/R control, where (n) and (m) represent an integer greater than one, and

a processor and memory electrically connected the input, output, control, and W/R terminals, the memory being configurable to include 2 (m) blocks, each block consisting of 2 (n) sub-blocks, and each sub block consisting of(n) bits, the method comprising:

setting a W/R control message to a value representing one of a read operation and a write operation;

communicating the W/R control message from the master communication module to the slave communication module via the bus;

communicating the W/R control message from the slave communication module to the processor via the W/R control terminal;

communicating an (m)-bit message from the master communication module to the slave communication module via the bus;

communicating the (m)-bit message from the slave communication module to the processor via the (m) control terminals;

communicating a first (n)-bit message from the master communication module to the slave communication module via the bus;

communicating the first (n)-bit message from the slave communication module to the processor via the (n)-output terminals;

at the processor and memory,

identifying one of the blocks with the (m)-bit message; and

identifying one of the sub-blocks of the identified block with the first (n)-bit message;

if the W/R control message is a value representing a read operation,

obtaining the identified sub-block;

communicating a second (n)-bit message including the obtained data from the processor to the slave communication module via the (n)-input terminals; and

communicating the second (n)-bit message from the slave communication module to the master communication module via the bus

if the W/R control message is a value representing a write operation

communicating a third (n)-bit message from the master communication module to the slave communication module via the bus,

communicating the third (n)-bit message from the slave communication module to the processor via the (n) output terminals,

writing the third (n)-bit message in the identified sub-block.

28. A method as set forth in claim 27 wherein the network further comprises a first (n) channels connecting the (n)-output terminals to the processor, a second (n) channels connecting the (n)-input terminals to the processor, (m) channels connecting the (m) control terminals to the processor, and a W/R channel connecting the W/R terminal to the processor, wherein the act of communicating the first (n)-bit message via the (n)-output terminals includes communicating each bit of the first (n)-bit message on a respective channel of the first (n) channels, wherein the act of communicating the second (n)-bit message via the (n)-input terminals includes communicating each bit of the second (n)-bit message on a respective channel of the second (n) channels, and wherein the act of communicating the third (n)-bit message via the (n)-output terminals includes communicating each bit of the third (n)-bit message on a respective channel of the second (n) channels.

29. A method as set forth in claim 27 wherein each block is identified binaryly from (0) to (m−1), and wherein the act of identifying one of the blocks includes identifying the block corresponding to the (m)-bit message, and wherein each sub-block is identified binaryly from (0) to (n−1), and wherein the act of identifying one of the sub-blocks includes identifying the sub-block corresponding to the first (n)-bit message.

30. A method as set forth in claim 27 wherein the bus is a two-wire bus, wherein the act of communicating a first (n)-bit message from the master communication module to the slave communication module includes the act of sequentially communicating the (n)-bits of the first (n)-bit message from the master communication module to the slave communication module, wherein the act of communicating the second (n)-bit message from the slave communication module to the master communication module includes the act of sequentially communicating the (n)-bits of the second (n)-bit message from the slave communication module to the master communication module, and wherein the act of communicating the third (n)-bit message from the slave communication module to the master communication module includes the act of sequentially communicating the (n)-bits of the third (n)-bit message from the slave communication module to the master communication module.

31. A method as set forth in claim 30 wherein the bus is an AS-Interface cable, and wherein the master communication module and slave communication module are compatible with the AS-Interface cable.

32. A method as set forth in claim 27 wherein (n) is equal to four and (m) is equal to two.

33. A method as set forth in claim 27 and further comprising the acts of

communicating a fourth (n)-bit message from the master communication module to the slave communication module;

communicating the fourth (n)-bit message from the slave communication module to the processor;

at the processor and memory, identifying a second sub-block of the identified block with the fourth (n)-bit message;

if the W/R control message is a value representing a read operation,

obtaining the second identified sub-block;

communicating a fifth (n)-bit message including the obtained data of the second identified sub-block from the processor to the slave communication module via the (n)-input terminals;

communicating the fifth (n)-bit message from the slave communication module to the master communication module via the bus;

at the master communication module,

storing at least a portion of the second (n)-bit message; and

combining the stored portion of the second (n)-bit message with at least a portion of the fifth (n)-bit message; and

if the W/R control message is a value representing a write operation,

providing a (p)-bit message, where (p) is an integer greater than (n);

decomposing the (p)-bit message to result in the third (n)-bit message and a sixth (n)-bit message, at least part of the third (n)-bit message being a portion of the (p)-bit message and at least part of the sixth (n)-bit message being a portion of the (p)-bit message;

communicating the sixth (n)-bit message from the master communication module to the slave communication module via the bus;

communicating the sixth (n)-bit message from the slave communication module to the processor via the output terminals; and

at the processor and memory, writing the sixth (n)-bit message in the identified second sub-block.