Data packing and unpacking engine
Systems and methods are disclosed to transfer data between a first bus internal to a system-on-chip (SOC) device and a second bus external to the SOC device, each bus having a plurality of bus segments shared among a plurality of peripheral devices communicating over one or more bus segments. When reading data from a peripheral device, the system packs data by enabling each effected first bus data segment in sequence until requested data is packed; and when writing data to a peripheral device, the system unpacks data by enabling each effected second bus data segment in sequence until requested data is unpacked.
1. An apparatus to transfer data between a first bus internal to a system-on-chip (SOC) device and a second bus external to the SOC device, each bus having a plurality of bus segments shared among a plurality of peripheral devices communicating over one or more bus segments, the apparatus comprising:
a packing unit positioned between the first and second buses, the packing unit comprising:
a flip-flop driving an effected first bus segment, and
a multiplexer coupled to the flip-flop, the multiplexer receiving data from a plurality of second bus segments and adapted to enable the effected first bus data segment in sequence; and
an unpacking unit positioned between the first and second buses, the unpacking unit comprising:
a multiplexer, the multiplexer receiving data from a plurality of first bus segments and adapted to enable an effected first bus data segment in sequence; and
a flip-flop coupled to the multiplexer to drive the effected second bus segment;
wherein the packing and unpacking units utilize gated clocks for packing and unpacking of data, wherein the gated clock is enabled based on a target peripheral device's width, location, and the least significant bits of the address for the target peripheral device.
2. The apparatus of claim 1 , wherein the flip-flop is a byte-wide flip-flop.
3. The apparatus of claim 1 , wherein the packing unit further comprises a plurality of byte-wide flip-flops having outputs connected to each segment of the first bus.
4. The apparatus of claim 3 , wherein each flip-flop is individually clocked.
5. The apparatus of claim 3 , further comprising a plurality of multiplexers coupled to each segment of the second bus and adapted to move data from any byte of the second bus to any arbitrary byte on the first bus.
6. The apparatus of claim 1 , wherein the unpacking unit further comprises a plurality of byte-wide flip-flops having outputs connected to each segment of the second bus.
7. The apparatus of claim 6 , further comprising a plurality of multiplexers coupled to the plurality of flip-flops and adapted to move data from any byte of the first bus to the input of each flip-flop.
8. The apparatus of claim 1 , wherein the unpacking unit writes to an 8-bit device that is arbitrarily connected to any byte of the second bus.
9. The apparatus of claim 1 , wherein the unpacking unit writes to any 16-bit device that is connected to two consecutive bytes of the second bus.
10. A data transfer apparatus adapted to transfer data between a first bus internal to a system-on-clip (SOC) device and a second bus external to the SOC device, each bus having a plurality of bus segments shared among a plurality of peripheral devices communicating over one or more bus segments, the apparatus comprising:
a packing unit positioned between the first and second buses, the packing unit adapted to enable each effected first bus data segment in sequence until requested data is packed; and
an unpacking unit positioned between the first and second buses, the unpacking unit adapted to enable each effected second bus data segment in sequence until requested data is unpacked;
wherein the packing and unpacking units utilize gated clocks for packing and unpacking of data, wherein the gated clock is enabled based on a target peripheral device's width, location, and the least significant bits of the address for the target peripheral device.
11. The apparatus of claim 10 , wherein the unpacking unit conserves power by driving only an effected segment of the second bus.
12. The apparatus of claim 10 , wherein the unpacking unit conserves the power by enabling a relative segment of the second bus, and holding the relative segment to transfer the captured data up-to the first bus's data width.
13. The apparatus of claim 10 , wherein each bus comprises four data segments.
14. A method to transfer data between a first bus internal to a system-on-chip (SOC) device and a second bus external to the SOC device, each bus having a plurality of bus segments shared among a plurality of peripheral devices communicating over one or more bus segments, the method comprising:
when reading data from the peripheral device, packing data by enabling each effected first bus data segment in sequence until requested data is packed;
when writing data to the peripheral device, unpacking data by enabling each effected second bus data segment in sequence until requested data is unpacked; and
gating clock signals for packing and unpacking of data, wherein the gating further comprises enabling a flip-flop based on a target peripheral device's width, location, and the least significant bits of the address for the target peripheral device.
15. The method of claim 14 , further comprising conserving power by driving only an effected data bus segment of the second bus.
16. The method of claim 14 , further comprising conserving power by:
enabling a relative segment of the data bus, and
holding the relative segment to transfer data up-to the first bus's data width.