Sea-of-cells array of transistors
View Patent ↗The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.
1. A method of constructing an integrated circuit that includes multiple physical layers of interconnect, the method comprising:
providing at least one physical layer of interconnect consisting essentially of local interconnect;
providing at least one physical layer of interconnect consisting essentially of global interconnect;
providing different spacings between adjacent interconnect traces on one of said physical layers;
providing a MACRO, for use as a part of the integrated circuit; and
utilizing a second layer of metallization comprising no local interconnect as part of said MACRO.
2. The method of claim 1 , wherein the MACRO is embedded in a standard cell array.
3. The method of claim 1 , further comprising:
providing an insulator layer at least partially between the at least one physical layer of interconnect consisting essentially of local interconnect and the at least one physical layer of interconnect consisting essentially of global interconnect.
4. The method of claim 3 , further comprising:
providing an insulator layer at least partially between the first physical layer of interconnect and the second physical layer of interconnect.
5. The method of claim 1 , wherein the at least one physical layer of interconnect consisting essentially of local interconnect comprises a first layer consisting essentially of local interconnect and a second layer consisting essentially of local interconnect.
6. The method of claim 1 , wherein the at least one physical layer of interconnect consisting essentially of global interconnect comprises a first layer consisting essentially of global interconnect and a second layer consisting essentially of global interconnect.
7. The method of claim 6 , further comprising:
providing an insulator layer at least partially between the first physical layer of interconnect and the second physical layer of interconnect.
8. A method of constructing multiple physical layers of interconnect in an integrated circuit, the method comprising:
providing a physical layer of interconnect comprising local interconnect and having no global interconnect;
providing a second physical layer of interconnect comprising local interconnect;
providing an insulator layer at least partially between the physical layer of interconnect and the second physical layer of interconnect;
providing a MACRO, for use as a part of the integrated circuit; and
utilizing a second layer of metallization comprising no local interconnect as part of said MACRO.
9. The method of claim 8 , wherein the MACRO is embedded within a standard cell array.
10. The method of claim 8 , further comprising:
providing different spacings between adjacent interconnect traces on one of said physical layers.
11. A method of constructing multiple physical layers of interconnect in an integrated circuit, the method comprising:
providing a physical layer of interconnect comprising local interconnect and having no global interconnect;
providing a second physical layer of interconnect comprising local interconnect;
providing a third physical layer of interconnect comprising global interconnect and comprising no local interconnect
providing a MACRO, for use as apart of the integrated circuit; and
utilizing a second layer of metallization comprising no local interconnect as part of said MACRO.
12. The method of claim 11 , wherein the MACRO is embedded within a standard cell array.
13. The method of claim 11 , further comprising:
providing an insulator layer at least partially between the physical layer of interconnect and the second physical layer of interconnect.
14. The method of claim 11 , further comprising:
providing an insulator layer at least partially between the second physical layer of interconnect and the third physical layer of interconnect.
15. The method of claim 11 , further comprising:
providing different spacings between adjacent interconnect traces on one of said physical layers.