Digital signal processing scheme for high performance HFC digital return path system with bandwidth conservation
View Patent ↗In a cable return path system, a method for performing digital companding adds a predetermined offset to the digital value to be companded, and employs a modified μ-law or a-law companding technique to obtain a reduced bit length digital value. One embodiment of this modified approach adds a predetermined offset (e.g., 129 for a 12-bit implementation) to the digital value before companding and then employs a two-bit chord and a 5-bit step for the 12-bit implementation. The end result is that the performance metrics are not significantly compromised by this bit reduction when compared to current transmission methods without this technique.
1. A method for companding a digital signal comprising:
adding an offset to the digital signal to form a biased digital signal; and
converting the biased digital signal to a shortened digital signal,
wherein the digital signal comprises one sign bit and eleven bits of magnitude the offset comprises a value of 129.
2. The method according to claim 1 , wherein the converting comprises a μ-law companding process.
3. The method according to claim 1 , wherein the converting comprises an a-law companding process.
4. A method for converting a 12-bit digital signal to a 7-bit digital signal comprising:
using a two-bit exponent and a 5-bit mantissa to represent the 12-bit digital signal when performing a companding process to seven bits; and
adding a predetermined offset to the digital signal before performing the companding process.
5. The method according to claim 4 , wherein the predetermined offset comprises a value of 129.
6. The method according to claim 4 , wherein the companding process comprises a μ-law companding process.
7. The method according to claim 4 , wherein the companding process comprises an a-law companding process.
8. A method for companding a digital input signal comprising:
adding a predetermined offset to the digital signal to obtain a biased input signal;
converting the biased input signal to a biased output signal by a companding process; and
subtracting the predetermined offset from the biased output signal to obtain a final digital output signal,
wherein the digital input signal comprises twelve bits, one of which includes a sign bit, and the sign bit is transferred to the final digital output signal.
9. A method for companding a digital input signal comprising:
adding a predetermined offset to the digital signal to obtain a biased input signal;
converting the biased input signal to a biased output signal by a companding process; and
subtracting the predetermined offset from the biased output signal to obtain a final digital output signal,
wherein the digital input signal comprises twelve bits, one of which includes a sign bit, and the predetermined offset comprises a value of 129.
10. The method according to claim 8 , wherein the companding process comprises a μ-law companding process.
11. A method for companding a digital input signal comprising:
adding a predetermined offset to the digital signal to obtain a biased input signal;
converting the biased input signal to a biased output signal by a companding process; and
subtracting the predetermined offset from the biased output signal to obtain a final digital output signal,
wherein the final digital output signal comprises eight bits, one of which includes a sign bit.
12. An apparatus for performing a companding process on a digital signal comprising:
a transmission processor receiving the digital signal and adding a predetermined offset to the digital signal to obtain a biased input signal;
a memory coupled to the transmission processor and storing a first lookup table with a mapping of a companding process from a first value to a second value,
wherein the first value has more bits than the second value, said transmission processor using the biased input signal to obtain a converted value in the first lookup table corresponding the biased input signal having fewer bits than the biased input signal and outputting the converted value for transmission over a communications channel.
13. The apparatus according to claim 12 , further comprising:
a receiver processor receiving the converted value from the communications channel; and
a memory coupled to the receiver processor and storing a second lookup table with a mapping of the companding process from a third value to a fourth value,
wherein the fourth value has more bits than the third value, said receiver processor using the received converted value to obtain an approximation of the biased input signal in the second lookup table corresponding the received converted value having more bits than the received converted value, subtracting the predetermined value from the approximation of the biased input signal and outputting a result as an approximation of the digital signal received over the communications channel.
14. The apparatus according to claim 12 , wherein the digital input signal comprises twelve bits, one of which includes a sign bit.
15. The apparatus according to claim 14 , wherein the sign bit is transferred to the final digital output signal.
16. The apparatus according to claim 12 , wherein the predetermined offset comprises a value of 129.
17. The apparatus according to claim 12 , wherein the companding process comprises a μ-law companding process.
18. The apparatus according to claim 12 , wherein the converted value comprises eight bits, one of which includes a sign bit.