Semiconductor integrated circuit device and process for manufacturing the same
View Patent ↗In a peripheral circuit region of a DRAM, two connection holes, for connecting a first layer line and a second layer line electrically are opened separately in two processes. After forming the connection holes, plugs are formed in the respective connection holes.
1. A semiconductor integrated circuit device including, on a semiconductor substrate, a plurality of memory cells each having a memory cell selecting transistor and an information storage capacitive element connected in series with said memory cell selecting transistor, the semiconductor integrated circuit device comprising:
a bit line and a first line formed in the same wiring layer over said semiconductor substrate; said information storage capacitive element provided over said bit line not through other wiring layers; and a second line provided over said information storage capacitive element,
wherein in the region other than the region where said memory cell is formed, there are provided a first plug connected in direct contact with said first line, and a second plug connected in direct contact with said first plug and said second line between said first line and said second line,
wherein said first line and said second line are electrically connected,
wherein a contact portion between said first plug and said second plug is higher than a lower end portion of said information storage capacitive element, and
wherein said contact portion between said first plug and aid second plug is lower than a higher end portion of said information storage capacitive element.
2. A semiconductor integrated circuit device according to claim 1 ,
wherein said second plug has a planar size larger than that of said first plug.
3. A semiconductor integrated circuit device according to claim 1 ,
wherein said first line is made of tungsten or tungsten silicide, and
wherein said first plug comprises a first metal film and a second metal film of tungsten overlying said first metal film and formed by a CVD method.
4. A semiconductor integrated circuit device including, on a semiconductor substrate, a plurality of memory cells each having a memory cell selecting transistor and an information storage capacitive element connected in series with said memory cell selecting transistor, the semiconductor integrated circuit device comprising:
(a) a first line and a bit line formed in the same wiring layer over said semiconductor substrate;
(b) a first insulation film covering said first line and said bit line;
(c) a first connection hole opened in the region other than said memory cell forming region such that a part of said first line is exposed in said first insulation film;
(d) a first plug formed by filling in said first connection hole with a conductor film;
(e) an information storage capacitive element formed over said bit line;
(f) a second line formed in a wiring layer over said information storage capacitive element;
(g) a second connection hole opened in the region other than said memory cell forming region, in the insulation film between said second line and said first plug such that said second connection hole overlies said second line in the plan view and a part of said first plug is exposed; and
(h) a second plug formed by filling in said second connection hole with a conductor film and electrically connected in direct contact with said second line and said first plug, wherein said first plug and said second plug are disposed between said first line and said second line,
wherein a contact portion between said first plug and said second plug is higher than a lower end portion of said information storage capacitive element, and
wherein said contact portion between said first plug and aid second plug is lower than a higher end portion of said information storage capacitive element.