Balanced circuit arrangement and method for linearizing such an arrangement
View Patent ↗The present invention relates to a balanced circuit arrangement and methods for linearizing and calibrating such a circuit arrangement wherein linearization is obtained by introducing a load imbalance between the output branches of the balanced circuit arrangement. Thus, a controllable extraneous imbalance is created between the output loads of the balanced circuit arrangement to thereby obtain a linearization by means of even-order non-linearity.
1. A balanced circuit arrangement comprising:
a) first transistor means coupled via first load means to a power source;
b) second transistor means coupled via second load means to said power source; and
c) linearity control means for linearizing said balanced circuit arrangement by adjusting said first and second load means into a load imbalance.
2. A circuit arrangement according to claim 1 , wherein said linearity control means are arranged to perform said adjustment by selectively switching load elements to at least one of said first and second load means.
3. A circuit arrangement according to claim 2 , wherein said load elements are weighted load elements.
4. A circuit arrangement according to claim 1 , wherein said linearity control mean comprise at least one input terminal for inputting a control signal.
5. A circuit arrangement according to claim 1 , wherein said balanced circuit arrangement is a double-balanced circuit arrangement.
6. A mixer circuit comprising a balanced circuit arrangement as claimed in claim 1 .
7. A mixer circuit according to claim 6 , wherein said mixer circuit is a Gilbert-cell multiplier.
8. A modulator and/or demodulator circuit comprising a balanced circuit arrangement as claimed in claim 1 .
9. A modulator and/or demodulator circuit according to claim 8 , wherein said modulator and/or demodulator circuit is an IQ modulator and/or demodulator.
10. A receiver and/or transmitter circuit comprising a balanced circuit arrangement as claimed in claim 1 .
11. A receiver and/or transmitter circuit according to claim 10 , wherein said receiver and/or transmitter circuit comprises a direct conversion receiver.
12. A method for linearizing a balanced circuit arrangement, comprising the steps of:
a) providing a controllable load means in at least one output branch of said balanced circuit arrangement; and
b) adjusting the load of said controllable load means to obtain a linearizing load imbalance in the output branches of said balanced circuit arrangement.
13. A method according to claim 12 , further comprising the step of canceling a DC voltage or lowpass filtered and averaged signal imbalance between said output branches after other distortion signals have been filtered out.
14. A method according to claim 12 , wherein said adjustment step is performed by selectively switching load elements of said controllable load means.
15. A method according to claim 14 , further comprising the step of providing said load elements with weighted load values.
16. A method for calibrating a balanced circuit arrangement, comprising the steps of:
a) measuring a DC output level or lowpass filtered level of said balanced circuit arrangement when no input signal is applied or when input signal changes have only a weak effect on the measured signal;
b) supplying a test signal to the input of said balanced circuit arrangement and measuring the DC output level;
c) determining a difference between said measured DC levels; and
d) adjusting a load means in at least one output branch of said balanced circuit arrangement until said determined difference is minimized.
17. A method according to claim 16 , wherein said adjusting step is an iterative step and said difference is monitored by a digital signal processing routine.
18. A method according to claim 16 , wherein said adjusting step is performed by selectively switching load elements of said load means.
19. A method according to claim 16 , wherein said calibrating method is used to calibrate a mixer circuit or modulator of a direct conversion receiver.