Frequency locked loop, clock recovery circuit and receiver

1. A frequency locked loop comprising a controllable oscillator ( 1 ) and a control signal generator ( 2 ) for generating a control signal (Sc) for the oscillator ( 1 ) from a reference signal (Sref) and an output signal (So) from the oscillator ( 1 ), characterized in that, the control signal generator ( 2 ) comprises:

a first chain including a high pass filter ( 21 ) and a non-linear processing unit ( 22 ) for generating a first intermediate signal (S 1 ) from the reference signal (Sref),

a second chain including a high pays filter ( 23 ) and a non-linear processing unit ( 24 ) for generating a second intermediate signal (S 2 ) from the output signal (So) of the controllable oscillator ( 1 ),

a combination unit ( 25 ) for generating a third intermediary signal (S 3 ) from the first (S 1 ) and the second intermediary signal (S 2 ),

a low-pass filter ( 26 ) for providing the control signal (Sc) in response to the third intermediary signal (S 3 ).

2. A frequency locked loop circuit according to claim 1 , characterized in that the combination unit ( 125 ) is coupled to the non-linear processing unit ( 122 ) of the first chain with a gain stage ( 125 a ).

3. A frequency locked loop circuit according to claim 1 , characterized in that the combination unit ( 125 ) is coupled to the non-linear processing unit ( 124 ) of the second chain with a gain stag ( 125 b ).

4. A frequency locked loop according to claim 1 , characterized in that the high pass filter ( 21 , 23 ) is a differentiator.

5. A frequency locked loop loop according to claim 1 , characterized in that the low pass filter ( 26 ) is an integrator.

6. A frequency locked loop according to claim 1 , characterize in that the non-linear processing unit ( 22 , 24 ) is an absolute value detector.

7. A frequency locked loop according to claim 4 , wherein the differentiator comprises a first ( 210 ) and a second circuit module ( 212 ) which are mutually coupled via a capacitive element (C).

8. A frequency locked loop according to claim 4 , characterized in that the differentiator comprises a translinear loop (Q 2 , Q 3 , Q 4 , Q 5 ).

9. A frequency locked loop according to claim 6 , characterized in that he absolute value detector ( 21 ) comprises a first circuit portion ( 221 ) for calculating the sign of the input signal and a second circuit portion ( 222 ) for multiplying the sign of the input signal with the momentaneous value of the input signal.

10. A clock recovery circuit comprising a controllable oscillator ( 1 ) which both is part of a frequency locked loop as claimed in claim 1 and of a phase locked loop.

11. A receiver ( 3 ) for a fibre-optic channel ( 5 ) comprising

an input ( 33 ) for receiving an input signal (Sin) from an sensor ( 4 ) which is coupled to the fibre-optic channel ( 5 ),

a clock recovery circuit ( 31 ) according to claim 10 coupled to the input ( 33 ) for receiving said input signal (Sin) as a reference signal,

a data recover circuit ( 32 ) coupled to said clock recovery circuit ( 31 ) and the input ( 33 ), for generating a digital output signal (Sout) in response to the input signal (Sin), and an output signal (CL) of the clock recovery circuit ( 31 ),

an output ( 34 ) or providing the digital output signal (Sout).