Semiconductor device and manufacturing method thereof
View Patent ↗Of three chips ( 2 A), ( 2 B), and ( 2 C) mounted on a main surface of a package substrate ( 1 ) in a multi-chip module (MCM), a chip ( 2 A) with a DRAM formed thereon and a chip ( 2 B) with a flash memory formed thereon are electrically connected to wiring lines ( 5 ) of the package substrate ( 1 ) through Au bumps ( 4 ), and a gap formed between main surfaces (lower surfaces) of the chips ( 2 A), ( 2 B) and a main surface of the package substrate ( 1 ) is filled with an under-fill resin ( 6 ). A chip ( 2 C) with a high-speed microprocessor formed thereon is mounted over the two chips ( 2 A) and ( 2 B) and is electrically connected to bonding pads ( 9 ) of the package substrate ( 1 ) through Au wires ( 8 ).
1. A semiconductor device comprising:
a wiring substrate having a main surface, a plurality of wiring lines and a plurality of electrode pads;
a first semiconductor chip having a main surface, a plurality of semiconductor elements and a plurality of electrodes, the first semiconductor chip being mounted over the main surface of the wiring substrate through a plurality of first bump electrodes in such a manner that the main surface of the first semiconductor chip is opposed to the main surface of the wiring substrate;
a second semiconductor chip having a main surface, a plurality of semiconductor elements and a plurality of electrodes, the second semiconductor chip being mounted over the main surface of the wiring substrate through a plurality of second bump electrodes in such a manner that the main surface of the second semiconductor chip is opposed to the main surface of the wiring substrate and that a side face of the second semiconductor chip is adjacent to a side face of the first semiconductor chip;
a third semiconductor chip having a main surface, a plurality of semiconductor elements and a plurality of electrodes, the third semiconductor chip being mounted over the first and second semiconductor chips in such a manner that a rear surface of the third semiconductor chip is opposed to rear surfaces of the first and second semiconductor chips;
a plurality of bonding wires electrically connecting the plurality of electrodes of the third semiconductor chip and the plurality of electrode pads respectively;
a first resin member sealing between the main surface of the first semiconductor chip and the main surface of the wiring substrate, between the main surface of the second semiconductor chip and the main surface of the wiring substrate, and between the side face of the first semiconductor chip and the side face of the second semiconductor chip; and
a second resin member sealing the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, part of the main surface of the wiring substrate, and part of the first resin member,
wherein the first resin member contains a first silica filler, the first silica filler having a first particle diameter,
the second resin member contains a second silica filler, the second silica filler having a second particle diameter, and
wherein the first particle diameter is smaller than the second particle diameter.
2. A semiconductor device according to claim 1 , wherein the first particle diameter is smaller than a distance between the side face of the first semiconductor chip and the side face of the second semiconductor chip.
3. A semiconductor device according to claim 2 , wherein the distance between the side face of the first semiconductor chip and the side face of the second semiconductor chip is about 20 to 60 μm.
4. A semiconductor device according to claim 1 , wherein the plurality of first bump electrodes and the plurality of the second bump electrodes are comprised of Au.
5. A semiconductor device according to claim 1 , wherein the first and the second semiconductor chips include a memory circuit having a plurality of memory elements, and the third semiconductor chip includes a microprocessor circuit adapted to operate in accordance with a program.
6. A semiconductor device according to claim 1 , wherein a DRAM or a flash memory is formed on the main surface of the first semiconductor chip.
7. A semiconductor device according to claim 1 , wherein the first particle diameter is about 70 to 100 μm, and the second particle diameter is about 3 μm.
8. A semiconductor device comprising:
a wiring substrate having a main surface, a plurality of wiring lines and a plurality of electrode pads;
a first semiconductor chip having a main surface, a plurality of semiconductor elements and a plurality of electrodes, the semiconductor chip being mounted over the main surface of the wiring substrate through a plurality of first bump electrodes in such a manner that the main surface of the first semiconductor chip is opposed to the main surface of the wiring substrate;
a second semiconductor chip having a main surface, a plurality of semiconductor elements and a plurality of electrodes, the second semiconductor chip being mounted over the main surface of the wiring substrate through a plurality of second bump electrodes in such a manner that the main surface of the second semiconductor chip is opposed to the main surface of the wiring substrate and side faces of the first and the second semiconductor chips are adjacent to each other;
a third semiconductor chip having a main surface, a plurality of semiconductor elements and a plurality of electrodes, the third semiconductor chip being mounted over the first and second semiconductor chips in such a manner that a rear surface of the third semiconductor chip is opposed to rear surfaces of the first and second semiconductor chips;
a plurality of bonding wires electrically connecting the plurality of electrodes of the third semiconductor chip and the plurality of electrode pads respectively;
a first resin member sealing between the main surface of the first semiconductor chip and the main surface of the wiring substrate, between the main surface of the second semiconductor chip and the main surface of the wiring substrate, and between the adjacent side faces of the first and second semiconductor chips; and
a second resin member sealing the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, part of the main surface of the wiring substrate and part of the first resin member;
wherein the first resin member contains a first silica filler, the first silica filler having a first particle diameter smaller than a distance between the adjacent side faces of the first and second semiconductor chips, and
wherein the second resin member contains a second silica filler, the second silica filler having a second particle diameter larger than the distance between the adjacent side faces of the first and second semiconductor chips.