Integrated digital circuit and a method for operating a digital circuit

1. An integrated digital circuit, comprising:

a line for transmitting data signals with several bits,

a coding unit for producing at least one derived data signal from a data signal to be transmitted over the line by changing the bit sequence of the data signal to be transmitted such that the derived signal contains the same bits as the data signal but arranged in a different order;

an evaluation unit for evaluating the susceptibility of the data signal and the derived data signal to interference caused by a capacitive coupling of the line with at least one neighboring line; and

a transmitter for outputting data signals onto the line, and which transmits the one of the data signal and the derived data signal which has been evaluated by the evaluation unit as having the least susceptibility to interference as caused by capacitive coupling.

2. The integrated digital circuit as claimed in claim 1 , further comprising a receiver for receiving the data signals transmitted over the line.

3. The integrated digital circuit as claimed in claim 2 , further comprising a decoding unit at the receiver end for determining the data signal to be transmitted from signals actually transmitted over the line.

4. The integrated digital circuit as claimed in claim 1 , in which the transmitter contains the coding unit.

5. The integrated digital circuit as claimed in claim 4 , in which the transmitter is designed for outputting the data signal to be transmitted and the derived data signal to the line, offset with respect to time.

6. The integrated digital circuit as claimed in claim 4 , further comprising a further line for transmitting data signals, in which the transmitter is designed for outputting the derived data signals to the further line.

7. The integrated digital circuit as claimed in claim 6 , in which the transmitter is designed for parallel output of the data signal to be transmitted to the line and of the derived data signal to the further line.

8. The integrated digital circuit as claimed in claim 4 , in which the transmitter contains the evaluation unit.

9. The integrated digital circuit as claimed in claim 2 , in which the receiver contains the evaluation unit.

10. The integrated digital circuit as claimed in claim 9 , in which the transmitter is designed to output an information signal, which specifies which exchange process was used to form the derived data signal from the signal to be transmitted.

11. The integrated digital circuit as claimed in claim 10 , in which the transmitter is designed for outputting the information signal to the line.

12. The integrated digital circuit as claimed in claim 10 , further comprising a further line for transmitting the information signal.

13. The integrated digital circuit as claimed in claim 1 , in which the transmitter is designed to output an information signal, specifying which exchange process was used to form the selected signal from the signal to be transmitted.

14. A method for operating an integrated digital circuit, comprising:

producing at least one derived data signal from a data signal to be transmitted over a line of the digital circuit by exchanging the bit sequence such that the derived signal contains the same bits as the data signal but arranged in a different order;

determining susceptibility of the data signal to be transmitted and the derived data signal to interference caused by capacitive coupling of the line to at least one neighboring line;

selecting from the data signal to be transmitted and each derived data signal that data signal which is least susceptible to interference as caused by capacitive coupling; and

transmitting the selected data signal on the line.

15. The method for operating an integrated digital circuit as claimed in claim 14 , in which the data signal to be transmitted and the derived data signal are transmitted over the line, offset with respect to time.

16. The method for operating an integrated digital circuit as claimed in claim 15 , in which the data signal to be transmitted is transmitted on the line and the derived data signal is transmitted on a further line.

17. The method for operating an integrated digital circuit as claimed in claim 14 , in which the susceptibility to interference of the data signal and of the derived data signal is determined in the receiver after transmission of the data signals over the line.

18. The method for operating an integrated digital circuit as claimed in claim 17 , in which the signal to be transmitted is determined from actually transmitted data signals with the help of the interference susceptibility determination.

19. The method for operating an integrated digital circuit as claimed in claim 14 , in which the susceptibility to interference of the data signal to be transmitted and each derived data signal is determined before a possible transmission.

20. The method for operating an integrated digital circuit as claimed in claim 14 , in which an information signal is output, specifying which exchange process was used to derive a transmitted signal from the signal to be transmitted.

21. The method for operating an integrated digital circuit as claimed in claim 20 , in which the information signal is transmitted on the line, offset with respect to time with respect to another data signal.

22. The method for operating an integrated digital circuit as claimed in claim 20 , in which the information signal is transmitted on a further line.

23. The method for operating an integrated digital circuit as claimed in claim 20 , in which the data signal to be transmitted is determined from an actually transmitted data signal or signals with the help of the transmitted information signal.