IP Library Granted Patent US 7,095,344
Granted Patent B2
US 7,095,344 · App. 10/480,046 · Granted Aug 22, 2006

Digital signal encoding device, digital signal decoding device, digital signal arithmetic encoding method and digital signal arithmetic decoding method

Assignee: Mitsubishi Denki Kabushiki Kaisha
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Quick Facts
Patent No.
US 7,095,344
App. No.
10/480,046
Granted
Aug 22, 2006
Kind
B2
Abstract

In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring in an arithmetic coding process, should be reset in the next transmission unit, an initial register value which indicates a register value to be used to start arithmetic coding/decoding to build/decompose the next transmission unit, only when the register reset flag indicates that the register should not be reset.

Claims (14)

1. A digital decoding apparatus for receiving and decoding a compression-coded digital signal received in predetermined units, comprising:

an arithmetic decoding unit for decoding the compressed digital signal received in the units according to an arithmetic coding process, wherein

said arithmetic decoding unit initializes a decoding process when decoding of a transmission unit is started, based on information multiplexed into data constituting the transmission unit and representing an arithmetic coding status.

2. The digital signal decoding apparatus according to claim 1 , wherein said arithmetic decoding unit decodes, by determining a probability of occurrence of restored symbols, based on dependence of the digital signal decoded on the signal included in one or a plurality of adjacent transmission units.

3. The digital signal decoding apparatus according to claim 1 , wherein said arithmetic decoding unit learns the probability by counting a frequency of restored symbols.

4. A digital decoding apparatus for receiving and decoding a compression-coded digital signal received in predetermined units, comprising:

an arithmetic decoding unit for decoding the compressed digital signal received in the units according to an arithmetic coding process, wherein

said arithmetic decoding unit initializes a decoding process when decoding of a transmission unit is started, based on information multiplexed into data constituting the transmission unit and representing an arithmetic coding status;

wherein the digital signal is a video signal and the transmission unit is a slice constituted by one or a plurality of macroblocks in a video frame.

5. A digital decoding apparatus for receiving and decoding a compression-coded digital signal received in predetermined units, comprising;

an arithmetic decoding unit for decoding the compressed digital signal received in the units according to an arithmetic coding process, wherein

said arithmetic decoding unit initializes a decoding process when decoding of a transmission unit is started, based on information multiplexed into data constituting the transmission unit and representing an arithmetic coding status;

wherein the digital signal is a video signal and the transmission unit is constructed by collecting coding data in a slice according to a type of the coding data.

6. The digital signal decoding apparatus according to claim 1 , wherein the digital signal is a video signal and the transmission unit is a video frame.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2020
From: MITSUBISHI ELECTRIC CORPORATION
To: XYLENE HOLDING S.A.
Reel/Frame 053905/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2003
From: SEKIGUCHI, SHUNICHI; YAMADA, YOSHIHISA; ASAI, KOHTARO
To: MITSUBIHSI DENKI KABUSHIKI KAISHA
Reel/Frame 015213/0759 →
Priority Claims (1)
JP 2002-124114 · Apr 25, 2002 · national
Continuity (1)
Related Publication 20040151252A1 · Aug 5, 2004