Single-wire communication bus for miniature low-power systems

1. A method for use in a system comprising a master and a slave connected by a single-wire asynchronous bus, the master operating in a first mode in which its clock is active and a second mode in which its clock is inactive, the method comprising the steps of:

in the master, entering the second mode;

at the slave, transmitting an interrupt comprising drawing the bus away from a quiescent level for a finite interval;

in the master, entering the first mode in response to the interrupt;

at the master, after entering the first mode, transmitting a start stage comprising at least three alternating bus states with at least one of the states having a duration defining a predetermined bit time; and

at the slave, determining the bit starting and ending times for the remaining bits of a transmission by detecting and analyzing the bus states of the start stage.

2. A method for use in a system comprising a master and a slave connected by a single-wire asynchronous bus, the slave operating in a first mode in which its clock is active and a second mode in which its clock is inactive, the method comprising the steps of:

in the slave, entering the second mode;

at the master, transmitting a start stage comprising at least three alternating bus states with at least one of the states having a duration defining a predetermined bit time;

in the slave, entering the first mode in response to the start stage; and

at the slave, determining the bit starting and ending times for the remaining bits of a transmission by detecting and analyzing the bus states of the start stage.

3. A method for use in a system comprising a master and a plurality of slaves, all connected by a single-wire asynchronous bus, each slave operating in a first mode in which its clock is active and a second mode in which its clock is inactive, the method comprising the steps of:

in each of the slaves, entering the second mode;

at the master, transmitting a start stage comprising at least three alternating bus states with at least one of the states having a duration defining a predetermined bit time;

in each of the slaves, entering the first mode in response to the start stage; and

at each of the slaves, determining the bit starting and ending times for the remaining bits of a transmission by detecting and analyzing the bus states of the start stage.

4. A method for use in a system comprising a master and a plurality of slaves, all connected by a single-wire asynchronous bus, each slave operating in a first mode in which its clock is active and a second mode in which its clock is inactive, each slave having a respective unique address, the method comprising the steps of:

at each of the slaves, entering the second mode;

at the master, transmitting a start stage comprising at least three alternating bus states with at least one of the states having a duration defining a predetermined bit time;

in each of the slaves, entering the first mode in response to the start stage;

at each of the slaves, determining the bit starting and ending times for the remaining bits of a transmission by detecting and analyzing the bus states of the start stage;

at the master, transmitting an addressing stage after the start stage, the addressing stage comprising a transmitted address;

at each of the slaves, receiving the transmitted address according to the determined bit time;

at each of the slaves, comparing the received address with the respective unique address thereof.

5. The method of claim 4 , further characterized in that in the event that one of the slaves finds a match between the received address and the respective unique address thereof, the one of the slaves responds to the master in a way differing from any of the other slaves.

6. The method of claim 4 , further characterized in that in the event that one of the slaves finds no match between the received address and the respective unique address thereof, the one of the slaves does not respond to the master.

7. The method of claim 4 , further comprising the steps of:

at the master, transmitting a data stage after the addressing stage, the data stage comprising transmitted data;

at one of the slaves, receiving the transmitted data according to the determined bit time.

8. The method of claim 7 , further comprising the steps of:

at the one of the slaves, confirming accurate receipt of the address and the data, and in the event of a match between the received address and the respective unique address, transmitting an acknowledgment on the bus according to the determined bit time.

9. The method of claim 4 , further comprising the steps of:

at one of the slaves, in the event of a match between the received address and the respective unique address, transmitting a data stage according to the determined bit time, the data stage comprising transmitted data; and

at the master, receiving the transmitted data according to the predetermined bit time.

10. A method for use in a system comprising a master and a plurality of slaves, all connected by a single-wire asynchronous bus, each slave having a respective unique address, the method comprising the steps of:

at the master, transmitting a start stage comprising at least three alternating bus states with at least one of the states having a duration defining a predetermined bit time;

at each of the slaves, determining the bit starting and ending times for the remaining bits of a transmission by detecting and analyzing the bus states of the start stage;

at the master, transmitting an addressing stage after the start stage, the addressing stage comprising a transmitted address;

at each of the slaves, receiving the transmitted address according to the determined bit time;

at each of the slaves, comparing the received address with the respective unique address thereof.

11. The method of claim 10 , further characterized in that in the event that one of the slaves finds a match between the received address and the respective unique address thereof, the one of the slaves responds to the master in a way differing from any of the other slaves.

12. The method of claim 10 , further characterized in that in the event that one of the slaves finds no match between the received address and the respective unique address thereof, the one of the slaves does not respond to the master.

13. The method of claim 10 , further comprising the steps of:

at the master, transmitting a data stage after the addressing stage, the data stage comprising transmitted data;

at one of the slaves, receiving the transmitted data according to the determined bit time.

14. The method of claim 13 , further comprising the steps of:

at the one of the slaves, confirming accurate receipt of the address and the data, and in the event of a match between the received address and the respective unique address, transmitting an acknowledgment on the bus according to the determined bit time.

15. The method of claim 10 , further comprising the steps of:

at one of the slaves, in the event of a match between the received address and the respective unique address, transmitting a data stage according to the determined bit time, the data stage comprising transmitted data; and

at the master, receiving the transmitted data according to the predetermined bit time.

16. A device for use with an asynchronous serial bus on which a start stage may be transmitted comprising at least three alternating bus states with at least one of the states having a duration defining a bit time, and on which an address stage comprising a plurality of address bits may subsequently be transmitted in accordance with the bit time and its phase, and on which a data stage may subsequently be transmitted in accordance with the bit time, the device having a unique address, the device comprising:

a line driver connected with the bus;

a line receiver connected with the bus;

means responsive to the line receiver for determining the bit starting and ending times for the remaining bits of a transmission by detecting and analyzing the bus states of the start stage;

means responsive to the line receiver for reading the address stage with respect to the determined bit time and deriving the address therefrom;

means comparing the derived address with the unique address, and

means responsive to the line receiver for reading the data stage with respect to the determined bit time and deriving the data therefrom.

17. The device of claim 16 wherein the reading of the data stage is performed only in the event of a match between the derived address and the unique address.

18. The device of claim 16 further comprising

means confirming accurate receipt by the device of the address and data, and

means transmitting an acknowledgment thereof by means of the line driver, in accordance with the determined bit time, only in the event of a match between the derived address and the unique address.

19. A device for use with an asynchronous serial bus on which a start stage may be transmitted comprising at least three alternating bus states with at least one of the states having a duration defining a bit time, and on which an address stage comprising a plurality of address bits may subsequently be transmitted in accordance with the bit time and its phase, the device having a unique address, the device comprising:

a line driver connected with the bus;

a line receiver connected with the bus;

means responsive to the line receiver for determining the bit starting and ending times for the remaining bits of a transmission by detecting and analyzing the bus states of the start stage;

means responsive to the line receiver for reading the address stage with respect to the determined bit time and deriving the address therefrom;

means comparing the derived address with the unique address, and

means responsive to a match between the derived address and the unique address for transmitting, by means of the line driver, a data stage with respect to the determined bit time.

20. A device for use with an asynchronous serial bus on which a start stage may be transmitted comprising at least three alternating bus states with at least one of the states having a duration defining a bit time, and on which an address stage comprising a plurality of address bits may subsequently be transmitted in accordance with the bit time and its phase, and on which a data stage may subsequently be transmitted in accordance with the bit time, the device having a unique address, the device operating according to a first mode in which an oscillator oscillates and according to a second mode in which it does not, the device comprising:

a line driver connected with the bus;

a line receiver connected with the bus;

means responsive to the line receiver for determining the bit starting and ending times for the remaining bits of a transmission by detecting and analyzing the bus states of the start stage;

means responsive to the line receiver for reading the address stage with respect to the determined bit time and deriving the address therefrom;

means comparing the derived address with the unique address;

means responsive to the line receiver for reading the data stage with respect to the determined bit time and deriving the data therefrom; and

means responding to a state change on the bus, in the event of the device being in the second mode, for causing a transition from the second mode to the first mode.

21. The device of claim 20 wherein the reading of the data stage is performed only in the event of a match between the derived address and the unique address.

22. The device of claim 20 further comprising

means confirming accurate receipt by the device of the address and data, and

means transmitting an acknowledgment thereof by means of the line driver, in accordance with the determined bit time, only in the event of a match between the derived address and the unique address.

23. A device for use with an asynchronous serial bus on which a start stage may be transmitted comprising at least three alternating bus states with at least one of the states having a duration defining a bit time, and on which an address stage comprising a plurality of address bits may subsequently be transmitted in accordance with the bit time and its phase, and on which a data stage may subsequently be transmitted in accordance with the bit time, the device having a unique address, the device operating according to a first mode in which an oscillator oscillates and according to a second mode in which it does not, the device comprising:

a line driver connected with the bus;

a line receiver connected with the bus;

means responsive to the line receiver for determining the bit starting and ending times for the remaining bits transmission, by detecting and analyzing the bus states of the start stage;

means responsive to the line receiver for reading the address stage with respect to the determined bit time and deriving the address therefrom;

means comparing the derived address with the unique address;

means responsive to a match between the derived address and the unique address for transmitting, by means of the line driver, a data stage with respect to the determined bit time; and

means responding to a state change on the bus, m the event of the device being in the second mode, for causing a transition from the second mode to the first mode.

24. A system comprising a master and a slave for use with an asynchronous serial bus;

the master comprising:

a line driver connected with the bus;

a line receiver connected with the bus;

means transmitting a start stage by means of the line driver, the start stage comprising at least three alternating bus states with at least one of the states having a duration defining a bit time;

means transmitting an address stage by means of the line driver after the start stage, the address stage comprising a plurality of address bits representing an address, in accordance with the bit time and its phase;

means transmitting a data stage by means of the line driver after the address stage, the data stage comprising a plurality of data bits representing data, in accordance with the bit time, the slave having a unique address,

the slave comprising:

a line driver connected with the bus;

a line receiver connected with the bus;

means responsive to the line receiver for determining the bit starting and ending times for the remaining bits of a transmission by detecting and analyzing the bus states of the start stage;

means responsive to the line receiver for reading the address stage with respect to the determined bit time and deriving the address therefrom;

means comparing the derived address with the unique address; and

means responsive to the line receiver for reading the data stage with respect to the determined bit time and deriving the data therefrom.

25. The system of claim 24 further characterized in that the reading of the data stage by the slave is performed only in the event of a match between the derived address and the unique address.

26. The system of claim 24 further characterized in that the master is operable in a first mode in which an oscillator oscillates and a second mode in which it does not, and in that the slave is operable in a first mode in which an oscillator oscillates and a second mode in which it does not,

the master further comprising means responsive to activity on the bus in the event the master is in the second mode for causing the master to enter the first mode,

the slave further comprising means responsive to activity on the bus in the event the slave is in the second mode for causing the slave to enter the first mode.

27. The system of claim 24 further comprising

means in the slave confirming accurate receipt by the slave of the address and data, and

means transmitting an acknowledgment thereof by means of the line driver thereof, in accordance with the determined bit time, only in the event of a match between the derived address and the unique address.

28. A system comprising a master and a slave for use with an asynchronous serial bus;

the master comprising:

a line driver connected with the bus;

a line receiver connected with the bus;

means transmitting a start stage by means of the line driver, the start stage comprising at least three alternating bus states with at least one of the states having a duration defining a bit time;

means transmitting an address stage by means of the line driver after the start stage, the address stage comprising a plurality of address bits representing an address, in accordance with the bit time and its phase;

the slave having a unique address, the slave comprising:

a line driver connected with the bus;

a line receiver connected with the bus;

means responsive to the line receiver for determining the bit starting and ending times for the remaining bits of a transmission by detecting and analyzing the bus states of the start stage;

means responsive to the line receiver for reading the address stage with respect to the determined bit time and deriving the address therefrom;

means comparing the derived address with the unique address; and

means responsive a match between the derived address and the unique address for transmitting, by means of the line driver, a data stage with respect to the determined bit time, the data stage comprising a plurality of data bits representing data;

the master further comprising:

means receiving the data stage by means of the line receiver after the address stage, in accordance with the bit time and its phase, and deriving the data therefrom.

29. A system comprising a master and a plurality of slaves for use with an asynchronous serial bus;

the master comprising:

a line driver connected with the bus;

a line receiver connected with the bus;

means transmitting a start stage by means of the line driver, the start stage comprising at least three alternating bus states with at least one of the states having a duration defining a bit time;

means transmitting an address stage by means of the line driver after the start stage, the address stage comprising a plurality of address bits indicative of an address in accordance with the bit time and its phase;

each slave having a unique address, each slave comprising:

a line driver connected with the bus;

a line receiver connected with the bus;

means responsive to the line receiver for determining the bit starting and ending times for the remaining bits of a transmission by detecting and analyzing the bus states of the start stage;

means responsive to the line receiver for reading the address stage with respect to the determined bit time and deriving the address therefrom; and

means comparing the derived address with the unique address, and

means responsive a match between the derived address and the unique address for transmitting, by means of the line driver, a data stage with respect to the determined bit time, the data stage comprising a plurality of data bits representing data;

the master further comprising:

means receiving the data stage by means of the line receiver after the address stage, in accordance with the bit time and its phase, and deriving the data therefrom.

30. A device for use with an asynchronous serial bus, the device comprising:

a line driver connected with the bus;

a line receiver connected with the bus;

means transmitting a start stage by means of the line driver, the start stage comprising at least three alternating bus states with at least one of the states having a duration defining a bit time;

means transmitting an address stage by means of the line driver after the start stage, the address stage comprising a plurality of address bits indicative of an address in accordance with the bit time and its phase;

means receiving a data stage comprising bits indicative of data by means of the line receiver after the address stage, in accordance with the bit time and its phase, and deriving the data therefrom.

31. A method for use with a device and an asynchronous serial bus, the method comprising the steps of:

transmitting a start stage by means of a line driver to the bus, the start stage comprising at least three alternating bus states with at least one of the states having a duration defining a bit time;

transmitting an address stage by means of the line driver after the start stage, the address stage comprising a plurality of address bits indicative of an address in accordance with the bit time and its phase;

receiving a data stage comprising bits indicative of data by means of a line receiver from the bus after the address stage, in accordance with the bit time and its phase, and

deriving the data therefrom.

32. A system comprising a master and a plurality of slaves for use with an asynchronous serial bus;

the master comprising:

a line driver connected with the bus;

a line receiver connected with the bus;

means transmitting a start stage by means of the line driver, the start stage comprising at least three alternating bus states with at least one of the states having a duration defining a bit time;

means transmitting an address stage by means of the line driver after the start stage, the address stage comprising a plurality of address bits representing an address, in accordance with the bit time and its phase;

means transmitting a data stage by means of the line driver after the address stage, the data stage comprising a plurality of data bits representing data, in accordance with the bit time,

each slave having a unique address, each slave comprising:

a line driver connected with the bus;

a line receiver connected with the bus;

means responsive to the line receiver for determining the bit starting and ending times for the remaining bits of a transmission by detecting and analyzing the bus states of the start stage;

means responsive to the line receiver for reading the address stage with respect to the determined bit time and deriving the address therefrom;

means comparing the derived address with the unique address; and

means responsive to the line receiver for reading the data stage with respect to the determined bit time and deriving the data therefrom.

33. The system of claim 32 further characterized in that the reading of the data stage by each slave is performed only in the event of a match between the derived address and the unique address.

34. The system of claim 32 further characterized in that the master is operable in a first mode in which an oscillator oscillates and a second mode in which it does not, and in that each slave is operable in a first mode in which an oscillator oscillates and a second mode in which it does not,

the master further comprising means responsive to activity on the bus in the event the master is in the second mode for causing the master to enter the first mode,

each slave further comprising means responsive to activity on the bus in the event the slave is in the second mode for causing the slave to enter the first mode.

35. The system of claim 32 further comprising

means in each slave confirming accurate receipt by the slave of the address and data, and

means transmitting an acknowledgment thereof by means of the line driver thereof, in accordance with the determined bit time, only in the event of a match between the derived address and the unique address.

36. A method for use in a system comprising a master and a slave connected by a single-wire asynchronous bus, the slave having a respective unique address, the method comprising the steps of:

at the master, transmitting a start stage comprising at least three alternating bus states with at least one of the states having a duration defining a predetermined bit time;

at the slave, determining the bit starting and ending times for the remaining bits of a transmission by detecting and analyzing the bus states of the start stage;

at the master, transmitting an addressing stage after the start stage, the addressing stage comprising a transmitted address;

at the slave, receiving the transmitted address according to the determined bit time;

at the slave, comparing the received address with the respective unique address thereof.

37. The method of claim 36 , further characterized in that in the event that the slave finds no match between the received address and the respective unique address thereof, the slave does not respond to the master.

38. The method of claim 36 , further comprising the steps of:

at the master, transmitting a data stage after the addressing stage, the data stage comprising transmitted data;

at the slave, receiving the transmitted data according to the determined bit time.

39. The method of claim 38 , further comprising the steps of:

at the slave, confirming accurate receipt of the address and the data, and in the event of a match between the received address and the respective unique address, transmitting an acknowledgment on the bus according to the determined bit time.

40. The method of claim 36 , further comprising the steps of:

at the slave, in the event of a match between the received address and the respective unique address, transmitting a data stage according to the determined bit time, the data stage comprising transmitted data; and

at the master, receiving the transmitted data according to the predetermined bit time.

41. A method for use with a device connected to a single-wire asynchronous bus at which a start stage comprising at least three alternating bus states with at least one of the states having a duration defining a predetermined bit time may be transmitted, and at which an addressing stage may be transmitted after the start stage, the addressing stage comprising a transmitted address, the device having a unique address, the method comprising the steps of:

determining the bit starting and ending times for the remaining bits of a transmission by detecting and analyzing the bus states of the start stage;

receiving the transmitted address according to the determined bit time; and

comparing the received address with the respective unique address thereof.

42. The method of claim 41 , in which a data stage may be transmitted after the addressing stage, the data stage comprising transmitted data, the method further comprising the steps of:

receiving the transmitted data according to the determined bit time.

43. The method of claim 42 , further comprising the steps of:

confirming accurate receipt of the address and the data, and in the event of a match between the received address and the respective unique address, transmitting an acknowledgment on the bus according to the determined bit time.

44. The method of claim 41 , further comprising the steps of:

in the event of a match between the received address and the respective unique address, transmitting a data stage according to the determined bit time, the data stage comprising transmitted data.