Method and circuit arrangement for memory error processing
View Patent ↗The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are recorded redundantly by applying a corresponding coding. Then, an error correction is applied to the faulty-address information before it is compared to an externally applied address. Thereby, errors due to faulty redundancy addresses can be prevented.
1. A method for performing error correction in a memory arrangement, said method comprising the steps of: a) determining a faulty-address information indicating an address of a faulty memory cell of said memory arrangement; b) adding redundancy by applying a coding to said faulty-address information; c) storing said coded faulty-address information; and d) applying an error processing to said coded faulty-address information before comparing said coded faulty-address information with an address used for addressing said memory arrangement.
2. A method according to claim 1 , wherein said error processing is an error correction processing.
3. A method according to claim 1 , wherein said coding is an error correction coding.
4. A method according to claim 1 , wherein said faulty-address information is read from a non-volatile memory ( 10 ) and stored in a volatile memory ( 22 ) at an initialization procedure.
5. A method according to claim 1 , wherein said redundancy is added by adding a predetermined number of error correction code bits to said faulty-address information.
6. A method according to claim 1 , wherein said error processing step comprises a decoding step for decoding said coded faulty-address information.
7. A circuit arrangement for performing an error correction in a memory arrangement, said circuit arrangement comprising: a) storing means ( 22 ) far storing a coded faulty-address information indicating an address of a faulty memory cell of said memory information; b) error processing means ( 24 ) for applying an error processing to said coded faulty-address information; and c) comparing means ( 26 ) for comparing said error-processed faulty-address information with an address used for addressing said memory arrangement.
8. A circuit arrangement according to claim 7 , wherein said storing means is a volatile memory ( 22 ).
9. A circuit arrangement according to claim 8 , wherein said volatile memory ( 22 ) is a latch, flip flop or SRAM memory.
10. A circuit arrangement according to claim 7 , wherein said circuit arrangement is arranged to read said coded faulty-address information from a non-volatile memory ( 10 ) at an initialization procedure.
11. A circuit arrangement according to claim 10 , wherein said non-volatile memory ( 10 ) comprises a fuse, antifuse or flash memory, an EPROM, an EEPROM, an FeRAM or an MRAM.
12. A circuit arrangement according to claim 7 , wherein said error processing means ( 24 ) is arranged to perform an error correction to said coded faulty-address information.