Interface circuit for connecting to an output of a frequency converter
View Patent ↗In an interface circuit for connection to an output of a frequency converter, at least two current paths are coupled to one another in parallel. Each current path includes at least one cascode stage for signal processing. The circuit compensates for DC voltage offsets of the frequency converter, and has a gain ratio that can be changed over for signals with a large dynamic range.
1. An interface circuit for connection to an output of a frequency converter, comprising:
a signal input;
a signal output;
a first current path, which couples the signal input to the signal output and comprises at least one cascode stage;
a second current path, which comprises a cascode stage connected in parallel with the cascode stage of the first current path;
one of the first and second current paths having a connection for receiving a common-mode signal; and
a third current path, which comprises a cascode stage coupled in parallel with the cascode stages of the first and second current paths, the cascode stages in the second and third current paths each having a control input connected to a bias stage that is operable for changing over between the second and third current paths.
2. The interface circuit as claimed in claim 1 , wherein the bias stage has an output coupled to the cascode stages in the first and second current paths for supplying bias voltage.
3. The interface circuit as claimed in claim 2 , wherein the bias stage has a control input and is responsive to a control signal at the control input thereof for putting the interface circuit into a current-saving mode.
4. The interface circuit as claimed in claim 3 , including a current divider which couples the signal output, the connection for providing a common-mode signal, and the cascode stage in the first current path.
5. The interface circuit as claimed in claim 2 , including a current divider which couples the signal output, the connection for providing a common-mode signal, and the cascode stage in the first current path.
6. The interface circuit as claimed in claim 1 , including a current divider which couples the signal output, the connection for providing a common-mode signal, and the cascode stage in the first current path.
7. The interface circuit as claimed in claim 6 , including a control loop for common-mode rejection, having a control input connected to the connection for providing a common-mode signal, and having an output coupled to the signal input.
8. The interface circuit as claimed in claim 7 , wherein the bias stage has an output coupled to the cascode stages in the first and second current paths for supplying bias voltage.
9. The interface circuit as claimed in claim 8 , wherein the bias stage has a control input and is responsive to a control signal at the control input thereof for putting the interface circuit into a current-saving mode.
10. The interface circuit as claimed in claim 1 , including a control loop for common-mode rejection, having a control input connected to the connection for providing a common-mode signal, and having an output coupled to the signal input.
11. The interface circuit as claimed in claim 10 , wherein the bias stage has an output coupled to the cascode stages in the first and second current paths for supplying bias voltage.
12. The interface circuit as claimed in claim 11 , wherein the bias stage has a control input and is responsive to a control signal at the control input thereof for putting the interface circuit into a current-saving mode.
13. The interface circuit as claimed in claim 12 , wherein the control loop for common-mode rejection comprises means for stabilizing the control loop.
14. The interface circuit as claimed in claim 13 , including a current divider which couples the signal output, the connection for providing a common-mode signal, and the cascode stage in the first current path.
15. The interface circuit as claimed in claim 11 , wherein the control loop for common-mode rejection comprises means for stabilizing the control loop.
16. The interface circuit as claimed in claim 15 , including a current divider which couples the signal output, the connection for providing a common-mode signal, and the cascode stage in the first current path.
17. The interface circuit as claimed in claim 10 , wherein the control loop for common-mode rejection comprises means for stabilizing the control loop.
18. The interface circuit as claimed in claim 17 , including a current divider which couples the signal output, the connection for providing a common-mode signal, and the cascode stage in the first current path.
19. The interface circuit as claimed in claim 1 , wherein the signal input, the signal output and the current paths are for processing symmetrical signals.