Semiconductor device and its manufacturing method, and electronic device
View Patent ↗The present invention proposes a semiconductor device, its manufacturing method and to an electronic apparatus thereof equipped with the semiconductor device where it becomes possible to make a CMOS type solid-state imaging device, an imager area formed with a MOS transistor of an LDD structure without having a metal silicide layer of a refractory metal, an area of DRAM cells and the like into a single semiconductor chip. According to the present invention, a semiconductor device is constituted such that an insulating film having a plurality of layers is used, sidewalls at the gate electrodes are formed by etching back the insulating film of the plurality of layers or a single layer film in the region where metal silicide layers are formed and in the region where the metal silicide layers are not formed, sidewalls composed of an upper layer insulating film is formed on a lower layer insulating film whose surface is coated or the insulating film of the plurality of layers remain unchanged.
1. A semiconductor device having a first region including a silicide layer and a second region without a silicide layer being formed, wherein
a sidewall composed of a plurality of insulating films which includes a first, second, and third insulating layer formed as lower, middle, and upper layers is formed at a side of a gate electrode of a first field effect transistor formed in said first region and said silicide layer is also formed at a source/drain region of said first field effect transistor, and
said second region includes a second field effect transistor and is covered by a plurality of insulating films which includes said first and second insulating layers, said second field effect transistor having a sidewall further comprised of said third upper insulating layer of said plurality of insulating films formed corresponding to a side of a gate electrode of said second field effect transistor such that said third upper insulating layer is formed exclusively as a sidewall of the gate electrode in said second region.
2. A semiconductor device according to claim 1 , wherein a silicide layer is formed at the gate electrode of the first field effect transistor formed in said first region.
3. A semiconductor device according to claim 1 , wherein said second insulating film is formed by an insulating film having a different etching characteristic from that of said third insulating film.
4. A semiconductor device according to claim 1 , wherein said first and third insulating films are silicon oxide films and said second insulating film is a silicon nitride film.
5. A semiconductor device according to claim 1 , wherein a film thickness of the silicon oxide film forming said first insulating film is selected to be 20 nm or less, a film thickness of the silicon nitride film forming said second insulating film is selected to be 30 nm or less and a film thickness of a silicon oxide film forming said third insulating film is selected to be 100 nm or less.
6. A semiconductor device according to claim 1 , wherein said first field effect transistor formed in said first region constitutes a logic circuit and a signal charge storing means is formed in said second region.
7. A semiconductor device having a first region including a silicide layer and a second region without a silicide layer being formed, wherein
a sidewall composed of a plurality of insulating films which includes a first, second, and third insulating layer formed as lower, middle, and upper layers is formed at a side of a gate electrode of a first field effect transistor formed in said first region and said silicide layer is also formed at a source/drain region of said first field effect transistor, and
said second region includes a second field effect transistor and is covered by a plurality of insulating films which includes said first and second insulating layers, said second field effect transistor having a sidewall further comprised of said third upper insulating layer of said plurality of insulating films formed corresponding to a side of a gate electrode of said second field effect transistor such that said third upper insulating layer is formed exclusively as a sidewall of the gate electrode in said second region; and
wherein the first field effect transistor formed in said first region constitutes a logic circuit, and an imager area having a picture element comprised of the second field effect transistor and a sensor portion is formed in said second region such that said semiconductor device is a CMOS type solid-state imaging device.
8. A semiconductor device according to claim 7 ,
wherein a plurality of insulating films which includes said first, second, and third insulating layers are stacked over said imager area; and
wherein said first insulating film is a silicon oxide film, said second film is a silicon nitride film, and said third film is a silicon nitride film; and wherein
a film thickness of the silicon oxide film of said first insulating film is selected to be 20 nm or less; and a total film thickness of the silicon nitride film of said second insulating film and the silicon nitride film of said upper layer insulating is selected to be between 150 nm and 20 nm.
9. A semiconductor device according to claim 1 , wherein the first field effect transistor formed in said first region constitutes a logic circuit, and a DRAM cell having a memory device comprising the second field effect transistor and a capacitance device is formed in said second region such that said semiconductor device is used as a logic semiconductor integrating circuit with embedded DRAM.