Semiconductor integrated circuit and its reset method
In a circuit block 110 to be an object of power-off, voltage detecting circuits 130 and 134 are disposed near power supply terminals 140 and 142 , respectively, and voltage detecting circuits 132 and 136 are disposed at given positions far from the terminals 140 and 142 , respectively, on power lines 141 and 143 of two electric-supply systems. The voltage detecting circuits are each made of MOS transistors only. At turning on the power from a power supply circuit 150 again, after all the voltage detecting circuits have detected arrival of power-supply voltages at a predetermined potential, a reset signal generating circuit 160 stops the input of a reset signal to the circuit block 110. Accordingly, since the reset state is stopped after the arrival of the power-supply voltages at the predetermined voltage, a semiconductor integrated circuit is initialized normally. This provides a semiconductor integrated circuit capable of generating a power-on reset signal appropriately.
1. A semiconductor integrated circuit, characterized by comprising:
a circuit block including a power line of at least one electrical system and a plurality of internal semiconductor devices to which power is supplied from the power line;
a plurality of voltage detecting means each connected to the power line at a given position on the power line and each outputting a voltage detection signal at a given potential when the potential at the given position on the power line is a predetermined potentials;
first power supply means for supplying or shutting off power to the circuit block in accordance with a power-supply control signal input from outside;
reset signal generating means for receiving the voltage detection signals from the plurality of voltage detecting means and outputting a reset signal to the circuit block when all the voltage detection signals from the plurality of voltage detecting means are not at the a given potential, while stopping the output of the reset signal to the circuit block after all the voltage detection signals are at the given potential; and
second power supply means for supplying power to the reset signal generating means.
2. The semiconductor integrated circuit of claim 1 , characterized in that each of the plurality of voltage detecting means includes voltage detecting means connected to the power line at a given position on the power line farthest from a starting point of power supply.
3. The semiconductor integrated circuit of claim 1 , characterized in that:
each of the plurality of voltage detecting means includes a p-MOS transistor and an n-MOS transistor;
the power line is connected to the drain of the p-MOS transistor;
the gate of the p-MOS transistor and the source and gate of the n-MOS transistor are grounded; and
the source of the p-MOS transistor is connected to the drain of the n-MOS transistor at a connection point, and the potential at the connection point is output as the voltage detection signal.
4. The semiconductor integrated circuit of claim 1 , characterized in that
the reset signal generating means includes:
a logic gate for receiving the voltage detection signals from the plurality of voltage detecting means and detecting that all the voltage detection signals are at the given potential; and
a delay unit for delaying the output of the logic gate by a given time,
wherein the output of the delay unit is output to the circuit block as the reset signal.
5. The semiconductor integrated circuit of claim 1 , characterized in that
the reset signal generating means includes:
a logic gate for receiving the voltage detection signals from the plurality of voltage detecting means and detecting that all the voltage detection signals are at the given potential; and
flip-flop circuits with a plurality of stages for sequentially delaying the output of the logic gate with a clock signal input from outside;
the output of the flip-flop circuit at the final stage is output to the circuit block as the reset signal.
6. The semiconductor integrated circuit of claim 1 , characterized in that the first power supply means and the second power supply means are integrated on a semiconductor substrate.
7. The semiconductor integrated circuit of claim 1 , characterized in that the circuit block and the reset signal generating means are integrated on a semiconductor substrate.
8. The semiconductor integrated circuit of claim 1 , characterized in that the circuit block, the reset signal generating means, the first power supply means and the second power supply means are integrated on a semiconductor substrate.
9. A semiconductor-integrated-circuit-resetting method for resetting, to an initial state, a circuit block provided in a semiconductor integrated circuit including: a power line of at least one electrical system; and the circuit block including a plurality of internal semiconductor devices to which power is supplied from the power line, the method being characterized in that:
power-supply potentials are detected at a plurality of positions on the power line;
whether or not all the power-supply potentials at the plurality of positions on the power line reach a predetermined potential is detected; and
a reset signal to be output to the circuit block is stopped when the result of the detection is true.
10. The semiconductor-integrated-circuit-resetting method of claim 9 , characterized in that:
an inverter including a p-MOS transistor and an n-MOS transistor is provided; and
the potentials on the power line are detected using a potential detecting circuit in which the drain of the p-MOS transistor is connected to the power line.