Logic circuit, timing generation circuit, display device, and portable terminal
View Patent ↗When a buffer is formed by using transistors having large element characteristic variations, the deviation of the timing between the input clock pulse and the reset pulse is likely to occur. When the deviation of the timing becomes larger, a malfunction is caused to occur, and an operation margin becomes smaller with respect to the variations of the element characteristics. In a timing generation circuit, which is formed on an insulating substrate and which has two TFFs ( 12, 13 ), for generating a dot clock DCK and a horizontal clock HCK whose frequencies are different in synchronization with a master clock MCK which is input external to the substrate, separate reset pulses drst and hrst are generated at a pulse generation circuit 15 with respect to the two TFFs ( 12, 13 ), and a resetting operation is performed at separate timings. Thus, a large operation margin can be ensured even when each circuit is formed by using TFTs having large element characteristic variations and a rough process rule.
1. A display device comprising:
a display section having pixels arranged in a matrix on a transparent insulating substrate; and
a timing generation circuit, mounted on said transparent insulating substrate together with said display section, for generating a plurality of timing signals whose frequencies are different, which are required to drive said display section, in synchronization with a master clock which is input external to the substrate,
wherein said timing generation circuit comprises:
a plurality of flip-flops, which are divided into at least two systems, for generating said plurality of timing signals in a corresponding manner; and
a reset circuit which separately resets said systems of flip-flops, at different timings.
2. A display device according to claim 1 , wherein said timing generation circuit is formed on said transparent insulating substrate by using low-temperature polysilicon or continuous-grain-boundary crystal silicon.
3. A portable terminal having incorporated therein a display device, said display device comprising:
a display section having pixels arranged in a matrix on a transparent insulating substrate; and
a timing generation circuit, mounted on said transparent insulating substrate together with said display section, for generating a plurality of timing signals whose frequencies are different, which are required to drive said display section, in synchronization with a master clock which is input external to the substrate,
wherein said timing generation circuit comprises:
a plurality of flip-flops, which are divided into at least two systems, for generating said plurality of timing signals in a corresponding manner; and
a reset circuit which separately resets said systems of flip-flops at different timings.