Providing current control over wafer borne semiconductor devices using overlayer patterns
View Patent ↗Disclosed are methods for providing wafer parasitic current control to a semiconductor wafer ( 1240 ) having a substrate ( 1240 ), at least one active layer ( 1240 ) and at least one surface layer ( 1240 ), Current control can be achieved through the formation of patterns ( 1240 ) surrounding contacts ( 1215 ), said patterns ( 1240 ) including insulating implants and/or sacrificial layers formed between active devices represented by said contacts ( 1215 ). Current flows through active regions ( 1260 ) associated with said contacts ( 1215 ) and active devices. Methods of and systems for wafer level burn-in (WLBI) of semiconductor devices are also disclosed. Current control at the wafer level is important when using WLBI methods and systems.
1. A method for providing wafer current control to electronic devices borne by a semiconductor wafer, comprising the steps of:
providing a semiconductor wafer having a substrate, at least one active layer, and a surface layer formed on said at least one active layer;
forming contacts on said surface layer such that said contacts are formed over each of a first plurality of regions in the semiconductor wafer; and
growing patterns on said surface layer such that said patterns are formed around but not over said contacts, wherein said patterns are configured to direct current flow away from a second plurality of regions in the semiconductor wafer when voltage is applied to said contacts and a common contact.
2. The method of claim 1 , wherein said patterns are diffusion patterns.
3. The method of claim 1 , wherein said patterns are metallization patterns.
4. The method of claim 1 , wherein said patterns are implant patterns.
5. The method of claim 1 , wherein said patterns are comprised of sacrificial material.
6. The method of claim 1 , wherein said patterns include dielectric patterns.
7. The method of claim 6 , wherein said dielectric patterns are selected from the group consisting of: nitride, oxide, polyimide, photoresist, and combinations thereof.
8. The method of claim 1 , further comprising the step of:
performing a wafer level burn-in procedure to said semiconductor wafer and electronic devices borne thereon.
9. The method of claim 1 , wherein said patterns are permanently bonded to said surface layer.
10. A method for providing wafer parasitic current control to a semiconductor wafer, comprising the steps of:
providing said semiconductor wafer having a substrate, active layers, and at least two contacts formed on a surface layer of the semiconductor wafer, wherein at least one active semiconductor device is defined by each of the at least two contacts and semiconductor layers formed between said at least two contacts and said substrate; and
growing patterns on said surface layer such that said patterns are formed over each of a first plurality of regions of the semiconductor wafer and are formed around but not over said at least two contacts; and
performing a wafer level burn-in procedure on said semiconductor wafer;
wherein said patterns are adapted to direct electrical current to flow within each of a second plurality of regions of the semiconductor wafer, defined as areas under the at least two contacts and extending through said at least one active semiconductor device, when voltage is applied to said at least two contacts and a common contact.
11. The method of claim 10 , wherein said patterns are diffusion patterns.
12. The method of claim 10 , wherein said patterns are metallization patterns.
13. The method of claim 10 , wherein said patterns are implant patterns.
14. The method of claim 10 , wherein said patterns are comprised of sacrificial material.
15. The method of claim 10 , wherein said patterns are dielectric patterns.
16. The method of claim 15 , wherein said dielectric patterns are selected from the group consisting of: nitride, oxide, polyimide, photoresist, and combinations thereof.