Method and device for synchronizing data transmission between two circuits

1. A method for synchronizing data transmission from a transmit circuit to a receive circuit, comprising:

in response to a first clock, the transmit circuit writing data into a buffer memory; in response to a second clock, the receive circuit reading the data from the buffer memory for further processing of the data;

comparing the first clock and second clocks;

in response to said comparing step, changing a phase relationship between the first and second clocks so that the first and second clocks are in phase with one another during said reading step, including adjusting an adjustable delay element to put the first and second clocks in phase with one another;

before said step of comparing the first and second clocks, comparing a divided version of the first clock to a divided version of the second clock and, in response to said step of comparing said divided versions of the first and second clocks, adjusting the adjustable delay element to put the divided versions of the first and second clocks in phase with one another.

2. The method of claim 1 , including deriving the first clock from the second clock, and providing the first clock to the receive circuit for at least one of said comparing steps.

3. The method of claim 1 , wherein said adjusting step includes using a loop filter which has a periodic characteristic curve.

4. The method of claim 3 , wherein said step of using a loop filter includes driving an up/down counter with an up/down count signal.

5. The method of claim 1 , including identifying a maximum delay between the second clock and the first clock, defining a first value that is greater by 1 than a ratio of the maximum delay to a period of the second clock, selecting a divisor value that is greater than the first value, and using the divisor value to produce the divided versions of the first and second clocks.

6. The method of claim 1 , wherein the transmit circuit is one of a CMOS circuit and a bipolar circuit, and the receive circuit is the other of a CMOS circuit and a bipolar circuit.

7. An apparatus for synchronizing data transmission from a transmit circuit to a receive circuit, comprising:

a buffer memory for storing data written thereto by a transmit circuit operating in response to a first clock, said buffer memory further for permitting the stored data to be read therefrom by the receive circuit operating in response to a second clock;

a phase detector for detecting a first phase relationship between the first and second clocks;

an adjustable delay element coupled to the phase detector and responsive to the first phase relationship for changing the first phase relationship so that the first and second clocks are in phase with one another when the data is read from the buffer memory; and

the phase detector further operable for detecting a second phase relationship between a divided version of the first clock and a divided version of the second clock and, before changing the first phase relationship, the adjustable delay element responsive to the second phase relationship for changing the second phase relationship to put the divided versions of the first and second clocks in phase with one another.

8. The apparatus of claim 7 , wherein the adjustable delay element is further for deriving the first clock from the second clock.

9. The apparatus of claim 8 , wherein the phase detector and the adjustable delay element are included in the receive circuit, and wherein the phase detector includes an input for receiving the first clock from the transmit circuit.

10. The apparatus of claim 7 , including a loop filter coupled between the adjustable delay element and the phase detector, the adjustable delay element driven by the phase detector via the loop filter.

11. The apparatus of claim 10 , wherein the phase detector provides an output signal indicative of one of the phase relationships, wherein the loop filter is for generating a loop filter output signal for setting a delay of the adjustable delay element, and wherein the loop filter has a periodic characteristic curve with regard to the phase detector output signal and the loop filter output signal.

12. The apparatus of claim 10 , wherein the loop filter includes an up/down counter, and the phase detector provides an output signal indicative of one of the phase relationships, and wherein the phase detector output signal is an up/down signal for driving the up/down counter.

13. The apparatus of claim 7 , wherein the transmit circuit is one of a CMOS circuit and a bipolar circuit, and the receive circuit is the other of a CMOS circuit and a bipolar circuit.

14. A device for synchronizing data transmission between first and second circuits comprising:

a first clock signal;

a second clock signal;

a buffer memory into which data is written by the first circuit in accordance with the first clock signal and out of which data is read by the second circuit in accordance with the second clock signal;

a phase detector for comparing the phase of the first clock signal with the phase of the second clock signal; and

an adjustable delay element responsive to the phase detector such that the phase of the first clock signal is changed according to the comparison made by the phase detector.

15. The device of claim 14 , wherein the first clock signal is derived from the adjustable delay element and from the second clock signal.

16. The device of claim 15 , wherein the phase detector and the adjustable delay element are in the second circuit and the first clock signal is in the first circuit and sent to the phase detector.

17. The device of claim 14 , wherein the adjustable delay element is driven via a loop filter by the phase detector.

18. The device of claim 17 , wherein the phase detector provides an output signal indicative of one of the phase relationships, wherein the loop filter is for generating a loop filter output signal for setting a delay of the adjustable delay element, and wherein the loop filter has a periodic characteristic curve with regard to the phase detector output signal and the loop filter output signal.

19. The device of claim 17 , wherein the loop filter includes an up/down counter, and the phase detector provides an output signal indicative of one of the phase relationships, and wherein the phase detector output signal is an up/down signal for driving the up/down counter.

20. The device of claim 14 , wherein the first circuit includes one or a CMOS circuit and a bipolar circuit and the second circuit includes the other of a CMOS circuit and a bipolar circuit.