RF converter with multiple mode frequency synthesizer compatible with a 48 Fo GPS baseband processor
View Patent ↗An RF-to-IF converter includes radio frequency (RF) to intermediate frequency (IF) processing circuitry and a frequency synthesizer for generating a local oscillator signal and clocking signals. The frequency synthesizer includes a local oscillator (LO) output coupled to the processing circuitry, a baseband processor clock output, and clock generation circuitry for generating a baseband processor clock with a frequency of approximately 48 fo on the baseband processor clock output, where fo is 1.023 MHz.
1. An RF-to-IF converter comprising:
radio frequency (RF) to intermediate frequency (IF) processing circuitry; and
a frequency synthesizer comprising:
a local oscillator (LO) output coupled to the processing circuitry;
a baseband processor clock output; and
clock generation circuitry coupled to the LO output, for generating a baseband processor clock with a frequency of approximately 48 fo on the baseband processor clock output, where fo is 1.023 MHz, wherein the clock generation circuitry further comprises a divide-by-2 counter and a multiplexer, the divide-by-2 counter comprising an input coupled to the output of the divide-by-32 counter and an output coupled to the multiplexer.
2. The RF-to-IF converter of claim 1 , wherein the frequency synthesizer further comprises a phase frequency detector (PFD), and wherein the multiplexer is coupled to the PFD.
3. The RF-to-IF converter of claim 1 , wherein the frequency synthesizer further comprises a frequency comparison output, and further comprising a phase frequency detector (PFD) coupled to the frequency comparison output.
4. The RF-to-IF converter of claim 3 , further comprising a frequency reference input coupled to the PFD.
5. The RF-to-IF converter of claim 4 , wherein the frequency reference input is coupled to the PFD through a programmable divider.
6. The RF-to-IF converter of claim 1 , further comprising a frequency reference input and wherein the clock generation circuitry comprises a programmable divide-by-n counter for producing the baseband processor clock from any of a pre-selected set of frequency references to be applied to the frequency reference input.
7. The RF-to-IF converter of claim 6 , wherein the pre-selected set of frequency references includes at least one of a 24 fo, 13 MHz, 15.36 MHz, 16.8 MHz, and 26 MHz frequency reference.
8. The RF-to-IF converter of claim 6 , wherein the pre-selected set of frequency references includes at least two of a 24 fo, 13 MHz, 15.36 MHz, 16.8 MHz, and 26 MHz frequency reference.
9. The RF-to-IF converter of claim 6 , wherein the programmable divide-by-n counter is a programmable fractional-n divider.
10. The RF-to-IF converter of claim 6 , wherein the programmable divide-by-n counter is a programmable integer-n divider.
11. The RF-to-IF converter of claim 6 , further comprising at least one programmable counter control input.