IP Library Granted Patent US 7,088,976
Granted Patent B2
US 7,088,976 · App. 10/492,390 · Granted Aug 8, 2006

Device for reconstructing data from a received data signal and corresponding transceiver

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Quick Facts
Patent No.
US 7,088,976
App. No.
10/492,390
Granted
Aug 8, 2006
Kind
B2
Abstract

In a transceiver which is configured in particular for transmitting optical data, there is provided a device for reconstructing data from a received data signal (RX), having a clock-signal recovery unit ( 3 ) for recovering a clock signal belonging to the transmitted data from the received data signal, and having a data reconstruction unit ( 2 ) for reconstructing the transmitted data from the received data signal using the recovered clock signal (f CLK ), and for emitting a data stream (DATA) which is synchronised with the recovered clock signal. A detector unit ( 9 ) detects an error state in the received data signal (RX) which prevents the data from being reconstructed reliably, switching means having a digital phase-locked lock ( 13 ) being provided to enable a signal having a clock rate which corresponds to the mean value of the clock signal (f CLK ) previously recovered by the clock-signal recovery unit ( 3 ) to be fed, as a reference signal, to a phase-locked loop of the clock-signal recovery unit ( 3 ) in this event in place of the received data signal, thus ensuring that the phase-locked loop of the clock-signal recovery unit ( 3 ) will continue to oscillate properly even in this event.

Claims (26)

1. A device for reconstructing data from a received data signal comprising:

a clock-signal recovery unit configured to generate a clock signal from the received data signal, the clock-signal recovery unit including a phase-locked loop to which the received data signal is fed as a reference signal and which produces the recovered clock signal in a phased-in state and a detector unit configured to detect an error state in the received data signal which prevents the data from being reliably reconstructed therefrom;

a data reconstruction unit configured to reconstruct the data from the received data signal using the recovered clock signal;

a switching network including a digital phase-locked loop, the switching network being coupled to the clock-signal recovery unit and configured, when the error state is detected, to provide to the phase-locked loop of the clock-signal recovery unit as its reference signal a signal having a clock rate that corresponds to a mean clock signal from the clock-signal recovery unit which was recovered over a given number of previous data transmissions; and

wherein the digital phase-locked loop is provided a signal derived from the recovered clock signal from the clock-signal recovery unit as a reference signal.

2. The device of claim 1 , wherein the detector unit is operably coupled to the phase-locked loop of the clock-signal recovery unit.

3. The device of claim 2 , wherein the detector unit includes a frequency comparator having an integrated error-state detecting means.

4. The device of claim 1 , wherein the phase-locked loop of the clock signal recovery unit includes a frequency divider and the detector unit configured to detect the error state analyzes an output signal from the frequency divider.

5. The device of claim 1 , wherein the digital phase-locked loop exhibits a pure integral-action controller characteristic.

6. The device of claim 1 , wherein the switching network includes a first and a second controllable switch controllably coupled to the detector unit and wherein an output of the digital phase-locked loop is connected to an input of the phase-locked loop of the clock-signal recovery unit via the first controllable switch and an input of the digital phase-locked loop is connected to an output of the phase-locked loop of the clock-signal recovery unit via the second controllable switch, the first controllable switch being opened and the second controllable switch being closed by the detector unit in a normal state, and the first controllable switch being closed and the second controllable switch being opened by the detector unit when the error state is detected.

7. The device of claim 1 , wherein the switching network comprises a compensator configured to compensate for abrupt phase shifts upon detection of the error state at a change to the signal of the mean recovered clock rate as a reference signal for the phase-locked loop of the clock-signal recovery unit.

8. The device of claim 7 , wherein the phase-locked loop of the clock-signal recovery unit includes a phase detector and the compensator analyzes an output signal of the phase detector to allow compensation for abrupt phase shifts.

9. The device of claim 1 , wherein the phase-locked loop of the clock-signal recovery unit comprises a digital phase detector, an analog oscillator which is controlled via an output of the digital phase detector and a digital frequency divider arranged in a feedback bath of the phase-locked loop.

10. The device of claim 9 , wherein the phase-locked loop of the clock-signal recovery unit further comprises an analog unit having a charge pump and a loop filter having an integral and proportional section, arranged between the digital phase detector and the analog oscillator.

11. The device of claim 9 , wherein the analog oscillator in the phase-locked loop of the clock-signal recovery unit comprises a current-controlled oscillator.

12. A transceiver for transmitting and receiving data signal over a transmission link, the transceiver comprising:

a receiving unit including a device for the reconstruction of data from a received data signal comprising;

a clock-signal recovery unit configured to recover a clock signal from the received data signal, the clock-signal recovery unit including a phase-locked loop to which the received data signal is fed as a reference signal and which produces the recovered clock signal in the phased-in state and a detector unit configured to detect an error state in the received data signal which prevents the data from being reliably reconstructed therefrom;

a data reconstruction unit configured to reconstruct the data from the received data signal using the recovered clock signal;

a switching network including a digital phase-locked loop, the switching network being coupled to the clock-signal recovery unit and configured, when the error state is detected, to provide to the phase-locked loop of the clock-signal recovery unit as its reference signal a signal having a clock rate that corresponds to a mean clock signal from the clock-signal recovery unit which was recovered over a given number of previous data transmissions, and

wherein the digital phase-locked loop is fed a signal derived from the recovered clock signal from the clock-signal recovery unit as a reference signal; and

a transmitting unit including a clock-signal generating unit configured to generate, as a function of the clock signal recovered by the clock-signal recovery unit, a transmission clock signal for a data signal to be transmitted.

13. The transceiver of claim 12 , wherein the clock signal recovered by the clock-signal recovery unit is provided via a frequency divider to the clock-signal generating unit as a reference signal.

14. The transceiver of claim 13 , wherein the switching network includes a first and a second controllable switch controllably coupled to the detector unit and wherein an output of the digital phase-locked loop is connected to an input of the phase-locked loop of the clock-signal recovery unit via the first controllable switch and an input of the digital phase-locked loop is connected to an output of the phase-locked loop of the clock-signal recovery unit via the second controllable switch, the first controllable switch being opened and the second controllable switch being closed by the detector unit in a normal state, and the first controllable switch being closed and the second controllable switch being opened by the detector unit when the error state is detected.

15. The transceiver of claim 13 wherein the phase-locked loop of the clock-signal recovery unit comprises a digital phase detector, an analog oscillator which is controlled via an output of the digital phase detector and a digital frequency divider arranged in a feedback bath of the phase-locked loop.

16. The transceiver of claim 12 , wherein the transceiver is equipped for the transmission of optical data.

Assignments (7)
MERGER AND CHANGE OF NAME Recorded Jan 17, 2018
From: LANTIQ DEUTSCHLAND GMBH; LANTIQ BETEILIGUNGS-GMBH & CO. KG
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 045086/0015 →
RELEASE OF SECURITY INTEREST RECORDED AT REEL/FRAME 025413/0340 AND 025406/0677 Recorded Apr 17, 2015
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 035453/0712 →
GRANT OF SECURITY INTEREST IN U.S. PATENTS Recorded Nov 29, 2010
From: LANTIQ DEUTSCHLAND GMBH
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 025406/0677 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2010
From: INFINEON TECHNOLOGIES WIRELESS SOLUTIONS GMBH
To: LANTIQ DEUTSCHLAND GMBH
Reel/Frame 024529/0635 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2010
From: INFINEON TECHNOLOGIES AG
To: INFINEON TECHNOLOGIES WIRELESS SOLUTIONS GMBH
Reel/Frame 024474/0958 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2004
From: GREGORIUS, PETER; HINZ, TORSTEN
To: INFINEON TECHNOLOGIES AG
Reel/Frame 016045/0629 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2004
From: GREGORIUS, PETER; HINZ, TORSTEN
To: INFINEON TECHNOLOGIES AG
Reel/Frame 015695/0491 →