High-resolution digital-to-analog converter

1. A digital/analog converter apparatus (DAC) for the linear conversion of a digital input signal (D) into an analog output signal (A), having

at least two digital/analog converters (DAC 1 , DAC 2 ),

a first unit (F 1 , F 2 ), which is connected upstream of the at least two digital/analog converters (DAC 1 , DAC 2 ) and is in a form such that it feeds inputs on the at least two digital/analog converters (DAC 1 , DAC 2 ) with digital intermediate signals (D 1 , D 2 ), coming from a digital input signal (D), and such that the digital intermediate signals (D 1 , D 2 ) are within prescribed ranges (I), and

a second unit (K 1 , K 2 , ADD), which is connected downstream of the at least two digital/analog converters (DAC 1 , DAC 2 ) and is a form such that it forms the analog output signal (A) from a linear combination of analog intermediate signals (A 1 , A 2 ) which can be tapped off at outputs on the at least two digital/analog converters (DAC 1 , DAC 2 ).

2. The digital/analog converter apparatus (DAC) as claimed in claim 1 , characterized

in that the first unit (F 1 , F 2 ) generates the digital intermediate signals (D 1 , D 2 ) through nonlinear digital signal processing of the digital input signal (D).

3. The digital/analog converter apparatus (DAC) as claimed in claim 2 , characterized

in that the first unit (F 1 , F 2 ) generates sawtooth-shaped digital intermediate signals (D 1 , D 2 ), particularly using a threshold value detector.

4. The digital/analog converter apparatus (DAC) as claimed in any one of the preceding claims, characterized

in that the at least two digital/analog converters (DAC 1 , DAC 2 ) have different gains and/or different resolutions.

5. The digital/analog converter apparatus (DAC) as claimed in any one of the preceding claims, characterized

in that the second unit (K 1 , K 2 , ADD) has, for each of the at least two digital/analog converters (DAC 1 , DAC 2 ), an amplifier for amplifying its analog intermediate signal (A 1 , A 2 ), with the amplifiers having different gain factors, in particular.

6. The digital/analog converter apparatus (DAC) as claimed in claim 5 , characterized

in that the second unit (K 1 , K 2 , ADD) is in a form such that it forms a difference and/or a sum for the amplified analog intermediate signals.

7. The digital/analog converter apparatus (DAC) as claimed in any one of claims 4 to 6 , characterized

in that the ratio of the gains of two respective digital/analog converters (DAC 1 , DAC 2 ) is approximately an integer.

8. The digital/analog converter apparatus (DAC) as claimed in any one of claims 4 to 7 , characterized

in that the ratio of the gains of two respective digital/analog converters (DAC 1 , DAC 2 ) is approximately equal to one.

9. The digital/analog converter apparatus (DAC) as claimed in any one of the preceding claims, characterized

in that the at least two digital/analog converters (DAC 1 , DAC 2 ) have different reference voltages.

10. The digital/analog converter apparatus (DAC) as claimed in any one of the preceding claims, characterized

in that the at least two digital/analog converters (DAC 1 , DAC 2 ) are based on the principle of series-connected resistors, with the at least two digital/analog converters (DAC 1 , DAC 2 ) having different numbers of series-connected resistors.

11. The digital/analog converter apparatus (DAC) as claimed in any one of claims 1 to 9 , characterized

in that the at least two digital/analog converters (DAC 1 , DAC 2 ) are based on the principle of series-connected resistors and have a common resistor chain.

12. The digital/analog converter apparatus (DAC) as claimed in any one of the preceding claims, characterized

in that the digital input signal (D) has more significant bits (B 5 , . . . , B 12 ) and less significant bits (B 0 , . . . , B 4 ), and

in that the first unit (F 1 , F 2 ) generates each digital intermediate signal (Dl, D 2 ) using a plurality of adders (ADDxy), the adders (ADDxy) being designed such that a first digital intermediate signal (D 1 ) is generated by adding the more significant bits (B 5 , . . . , B 12 ) to the less significant bits (B 0 , . . . , B 4 ), and that a second digital intermediate signal (D 2 ) is generated by adding the more significant bits (B 5 , . . . , B 12 ) to the inverted less significant bits (B 0 , . . . , B 4 ).

13. The digital/analog converter apparatus (DAC) as claimed in any one of the preceding claims, characterized

in that the at least two digital/analog converters (DAC 1 , DAC 2 ), the first unit and the second unit are integrated on a common substrate.

14. A method for the linear conversion of a digital input signal (D) into an analog output signal (A), having the following method steps:

(1) a first digital intermediate signal (D 1 ) and a second digital intermediate signal (D 2 ) are generated through digital signal processing of the digital input signal (D), with the two digital intermediate signals (D 1 , D 2 ) being generated such that they are within prescribed ranges (I);

(2) the first digital intermediate signal (D 1 ) is subjected to digital/analog conversion to give a first analog intermediate signal (A 1 ), and the second digital intermediate signal (D 2 ) is subjected to digital/analog conversion to give a second analog intermediate signal (A 2 ); and

(3) the analog output signal (A) is generated from linear combination of the two analog intermediate signals (A 1 , A 2 ).

15. The method as claimed in claim 14 , characterized

in that the two digital intermediate signals (Dl, D 2 ) are generated through nonlinear digital signal processing of the digital input signal (D).

16. The method as claimed in claim 15 , characterized

in that the two digital intermediate signals (D 1 , D 2 ) are sawtooth-shaped.

17. The method as claimed in any one of claims 14 to 16 , characterized

in that the two digital intermediate signals (D 1 , D 2 ) are converted into the two analog intermediate signals (A 1 , A 2 ) using different gains and/or using different resolutions.

18. The method as claimed in any one of claims 14 to 17 , characterized

in that method step (3) involves the two analog intermediate signals (A 1 , A 2 ) being amplified, this being done using different gain factors, in particular.

19. The method as claimed in claim 18 , characterized

in that method step (3) involves a sum and/or a difference for the two amplified analog intermediate signals (A 1 , A 2 ) being formed.

20. The metbod as claimed in any one of claims 17 to 19 , characterized

in that the ratio of the gains of the two digital intermediate signals (D 1 , D 2 ) during the digital/analog conversion is approximately an integer.

21. The method as claimed in any one of claims 17 to 20 , characterized

in that the ratio of the gains of the two digital intermediate signals (D 1 , D 2 ) during the digital/analog conversion is approximately equal to one.