Communication semiconductor integrated circuit device and a wireless communication system
View Patent ↗In one embodiment, a PLL circuit is provided with a plurality of pull-in operation modes for pulling a voltage across a filter capacitor (C 1 , C 2 ) in a lock-up voltage, and with a register (CRG) for designating one of the plurality of pull-in operation modes. The pull-in operation is performed in accordance with a setting value in the register.
1. A communication semiconductor integrated circuit device with a PLL circuit having a phase detecting circuit for detecting a phase difference between a signal having a predetermined frequency and a feedback signal, a charge pump and a filter capacitor for generating a voltage corresponding to the phase difference detected by the phase detecting circuit, and an oscillator circuit for performing an oscillation operation in accordance with the voltage across the filter capacitor, comprising first and second registers which output control values set therein,
wherein
the charge pump includes a plurality of first current sources which are controlled in accordance with outputs of the phase detecting circuit, and a plurality of second current sources which are controlled in accordance with outputs of the first and second registers,
in the first register, the control value for selecting one of the second current sources to be turned on is set,
in the second register, the control value for selecting an initial voltage at start-up of the PLL circuit is set,
the PLL circuit has a plurality of pull-in operation modes which are controlled in accordance with the outputs of the first and second registers, for pulling the voltage across the filter capacitor in a lock-up voltage in response to an activation of the PLL circuit, and performs the pull-in operation in accordance with a setting value in the first register for designating one of the plurality of pull-in operation modes.
2. A communication semiconductor integrated circuit device according to claim 1 , wherein at least one of the plurality of pull-in operation modes is an operation mode of starting the pull-in operation at a predetermined initial voltage lower than the lock-up voltage.
3. A communication semiconductor integrated circuit device according to claim 2 , wherein at least one of the plurality of pull-in operation modes is an operation mode of raising the voltage across the filter capacitor to a predetermined voltage higher than the lock-up voltage and thereafter gradually lowering the voltage across the filter capacitor.
4. A communication semiconductor integrated circuit device according to claim 2 , wherein the PLL circuit can select one of a plurality of levels as the initial voltage and the second register designates one of the plurality of levels.
5. A communication semiconductor integrated circuit device according to claim 4 , wherein a first current source for charging up the voltage across the filter capacitor at a start-up time and a second current source for charging up the voltage across the filter capacitor are provided, the second current source flows a current larger than a current flowing from the first current source, a time during which the second current source charges up the voltage across the filter capacitor is changed with a setting value in the second register.
6. A communication semiconductor integrated circuit device according to claim 1 , wherein the signal having the predetermined frequency is a modulated signal obtained by modulating a signal having a first frequency by transmission data, and the feedback signal is a signal which is output from a mixer for synthesizing an oscillation signal of the oscillator circuit and a signal having a second frequency higher than the first frequency and which has a frequency equal to a difference between a frequency of the oscillation signal and the frequency of the signal having the second frequency.