Mask for crystallizing polysilicon and a method for forming thin film transistor using the mask
View Patent ↗A mask for forming polysilicon has a first slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a second slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a third slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, and a fourth slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width. The slit patterns arranged at the first to fourth slit regions are sequentially enlarged in width in the horizontal direction in multiple proportion to the width d of the slit pattern at the first slit region. The centers of the slit patterns arranged at the first to fourth slit regions in the horizontal direction are placed at the same line. The slit patterns arranged at the respective slit regions in the vertical direction are spaced from each other with a distance of 8*d. Alternatively, the first to fourth slit regions may be arranged in reverse order, or in the vertical direction.
1. A method of fabricating a thin film transistor, the method comprising the steps of:
depositing an amorphous silicon layer onto an insulating substrate;
forming a semiconductor layer through crystallizing the amorphous silicon layer through a sequential lateral solidification process using a polysilicon formation mask where slit patterns for defining light transmission regions are arranged while being sequentially reduced or enlarged in width in a predetermined direction;
forming a gate insulating layer on the substrate such that the gate insulating layer covers the semiconductor layer;
forming a gate electrode on the gate insulating layer over the semiconductor layer;
forming source and drain regions at the semiconductor layer through implanting impurities into the semiconductor layer;
forming an inter-layered insulating layer such that the inter-layered insulating layer covers the gate electrode;
etching the inter-layered insulating layer and the gate insulating layer to thereby form contact holes exposing the source and the drain regions; and
forming source and drain electrodes such that the source and the drain electrodes are connected to the source and the drain regions through the contact holes.
2. The method of claim 1 , further comprising the step of forming a pixel electrode such that the pixel electrode is connected to the drain electrode.
3. The method of claim 2 , wherein the pixel electrode is formed with a transparent conductive material or a reflective conductive material.
4. The method of claim 1 , wherein the slit patterns are arranged at two or more different regions such that the slit patterns at the same region have the same width, and the sequential lateral solidification process is made while moving the mask by the width of each region in the predetermined direction.