Semiconductor device method of generating semiconductor device pattern method of semiconductor device and pattern generator for semiconductor device
View Patent ↗It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit. The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.
1. A semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region of the semiconductor device to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type; and
a substrate contact formed under a ground wiring region and fixing a substrate potential,
wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and includes the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other, and
wherein the bypass capacitor comprises capacitive insulating films which are different from each other and is formed in such a manner that a capacity per unit area is varied in a chip.
2. A semiconductor device comprising a first bypass capacitor including an MOS structure formed under a power wiring region of the semiconductor device and having a first gate electrode formed on a first diffusion region having a first conductivity type through a capacitive insulating film so as to be connected to a power wiring, the first gate electrode being connected to a necessary diffusion potential for forming a transistor capacity of the bypass capacitor on the ground wiring side; and
a second bypass capacitor including an MOS structure formed under a ground wiring region and having a second gate electrode formed on a second diffusion region having a different conductivity type from that of the first diffusion region through a capacitive insulating film so as to be connected to a ground wiring, the second gate electrode being connected to a necessary diffusion potential for forming a transistor capacity of the bypass capacitor on the power wiring side.
3. The semiconductor device according to claim 2 , wherein the power wiring is extended toward the ground wiring side at an edge on the ground wiring side and is connected to the second diffusion region, and
the ground wiring is extended toward the power wiring side at an edge on the power wiring side and is connected to the first diffusion region.
4. The semiconductor device according to claim 3 , wherein the power wiring and the ground wiring are mutually protruded to take a shape of a comb-tooth on a boundary thereof.
5. The semiconductor device according to claim 2 , wherein the first and second diffusion regions are mutually protruded to take a shape of a comb-tooth on a boundary between the power wiring side and the ground wiring side.
6. The semiconductor device according to claim 2 , wherein the first gate electrode of the first bypass capacitor has a wiring extended from the ground wiring side to the power wiring side at an edge on the ground wiring side and is connected to the second diffusion region, and
the second gate electrode of the second bypass capacitor has a wiring extended from the power wiring side to the ground wiring side at an edge on the power wiring side and is connected to the first diffusion region.
7. The semiconductor device according to claim 6 , wherein the first and second gate electrodes are mutually protruded to take a shape of a comb-tooth on a boundary between the power wiring side and the ground wiring side.
8. The semiconductor device according to any of claims 2 to 7 , wherein at least one of the first bypass capacitor and the second bypass capacitor has the first or second gate electrode provided with an opening portion for forming a contact region, and a contact of the first or second diffusion region is formed through the opening portion.
9. The semiconductor device according to claim 2 , wherein a connection of the first gate electrode and the second diffusion region and a connection of the second gate electrode and the first diffusion region are carried out through a joint cell unit.