IP Library Granted Patent US 7,321,959
Granted Patent B2
US 7,321,959 · App. 10/496,622 · Granted Jan 22, 2008

Control method of a non-volatile memory apparatus

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Quick Facts
Patent No.
US 7,321,959
App. No.
10/496,622
Granted
Jan 22, 2008
Kind
B2
Abstract

A control method of a non-volatile memory apparatus, which can execute data writing normally after the next startup even when a process is interrupted because of the occurrences of abnormal conditions such as power shut down during data writing or data erasing is provided. The control method of a non-volatile memory apparatus of the present invention comprises: a first flag writing step of writing a fixed value, which indicates that data is written, on a first flag existing in a redundancy area on a first page of a physical block and indicating whether or not data is written on the first page; and a data writing step of writing data on the physical block, when the data is written on the non-volatile memory consisting of a plurality of physical blocks.

Claims (18)

1. A control method of a non-volatile memory apparatus comprising:

a controlling step of controlling data writing and data readout of a non-volatile memory, by using an erased table and a logical address/physical address conversion table, the non-volatile memory having a plurality of physical blocks, each physical block being an erasing unit of data, the erased table indicating whether the physical blocks are erased or not, the logical address/physical address conversion table converting a logical address to a physical address;

a writing step; the writing step of including:

a first flag writing step of writing a fixed value on a first flag existing in a redundancy area on a first page of a physical block onto which data is to be written, a value of said first flag indicating whether data is to be written onto the first page of the physical block or not, the first page being within a plurality of pages which are included in said physical block, each page having a data area and the redundancy area, and each page being a minimum data writing unit, the first flag being included in each physical block; and

a data writing step of writing data onto the first page after the first flag writing step; and

an initialization step of reading out said first flag of all said physical blocks of said non-volatile memory at the startup of the non-volatile memory apparatus, and generating the logical address/physical address conversion table and the erased table based on whether said first flag is written or not.

2. A control method of a non-volatile memory apparatus comprising:

a controlling step of controlling data writing and data readout of a non-volatile memory, by using an erased table and a logical address/physical address conversion table, the non-volatile memory having a plurality of physical blocks, each physical block being an erasing unit of data, the erased table indicating whether the physical blocks are erased or not, a the logical address/physical address conversion table converting a logical address to a physical address;

a writing step; the writing step of including:

a first flag writing step of writing a fixed value on a first flag existing in a redundancy area on a first page of a physical block onto which data is to be written, a value of the first flag indicating whether data is written onto the first page of the physical block or not, the first page being within a plurality of pages which are included in said physical block, each page having a data area and the redundancy area, and each page being a minimum data writing unit, the first flag being included in each physical block;

a data writing step of writing data from the first page to the last page included in the physical block after the first flag writing step; and

a second flag writing step of writing a fixed value on a second flag existing in the redundancy area on a pre-determined page of said physical block and indicating whether writing data onto the physical block is completed or not after the data writing step; and

an initialization step of reading out said first flags and said second flags of all said physical blocks of the non-volatile memory at the startup of said non-volatile memory apparatus, and generating the logical address/physical address conversion table and the erased table based on whether said first flag and said second flag is written or not.

3. The control method of a non-volatile memory apparatus in accordance with claim 1 , further comprising:

a writing step of writing an ECC code and/or a CRC code of data of a last page, or these codes as well as complementary data of the ECC code and/or the CRC code onto the redundancy area of the last page when writing data on the physical block; and

an initialization step of reading out data and the ECC codes and/or the CRC codes of the data, or these data and codes as well as complementary data of the ECC code and/or the CRC code, from the last pages of all of said physical blocks of said non-volatile memory, executing an error detection, and generating the logical address/physical address conversion table based on presence or absence of an error at the startup of said non-volatile memory apparatus.

4. The control method of a non-volatile memory apparatus in accordance with claim 1 , further comprising a last page writing step of writing data onto all addresses of an area of a last page of said physical block, excluding an area for writing data which can be written singularly and separately, and filling the area with data and an ECC code and/or a CRC code of said data, or filling it with these data and codes as well as complementary data of the ECC code and/or the CRC code.

5. The control method of a non-volatile memory apparatus in accordance with claim 4 , further comprising an initialization step of reading out said data and said ECC codes and/or the CRC codes of said data, or these data and codes as well as complementary data of the ECC code and/or the CRC code, of the last pages of all said physical blocks of said non-volatile memory, executing an error detection, and generating the logical address/physical address conversion table based on presence or absence of an error at the startup of said non-volatile memory apparatus.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2014
From: PANASONIC CORPORATION (FORMERLY MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.)
To: GODO KAISHA IP BRIDGE 1
Reel/Frame 032209/0630 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2004
From: HONDA, TOSHIYUKI; TOYAMA, MASAYUKI; SAKAI, KEISUKE
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 015818/0701 →