Wire for a display device, a method for manufacturing the same, a thin film transistor array panel including the wire, and a method for manufacturing the same
View Patent ↗First, a Cr film and a CrOx film are deposited and patterned using an etchant including 8-12% Ce(NH 4 ) 2 (NO3) 6 , 10-20% NH 3 and remaining ultra pure water to form a gate wire including a plurality of gate lines, a plurality of gate electrodes and a plurality of gate pads. Next, a gate insulating film, a semiconductor layer and an ohmic contact layer are formed in sequence. A Cr film and CrOx film are deposited in sequence and patterned using an etchant including 8-12% Ce(NH 4 ) 2 (NO 3 ) 6 , 10-20% NH 3 and remaining ultra pure water to form a data wire including a plurality of data lines, a plurality of source electrodes, a plurality of drain electrodes and a plurality of data pads. A passivation layer is deposited and patterned to form a plurality of contact holes respectively exposing the drain electrodes, the gate pads and the data pads. A transparent conductive material or a reflective conductive material is deposited and patterned to form a plurality of pixel electrodes, a plurality of subsidiary gate pads and a plurality of subsidiary data pads electrically connected to the drain electrodes, the gate pads and the data pads, respectively. The gate lines and the data lines with low reflectance are used as a light-blocking film for blocking the light leakage between the pixel areas, and do not increase the black brightness. Accordingly, a separate black matrix need not be provided on the color filter panel, thereby securing both aperture ratio of the pixel and high contrast ratio.
1. A thin film transistor array panel comprising:
a gate wire formed on an insulating substrate and including a gate line and a gate electrode connected to the gate line;
a gate insulating film covering the gate wire;
a semiconductor layer formed on the gate insulating film;
a data wire formed on the gate insulating film or the semiconductor layer and including a data line, a source electrode connected to the data line and located on the semiconductor layer and a drain electrode formed on the semiconductor layer and located opposite the source electrode with respect to the gate electrode;
a passivation layer covering the data wire; and
a pixel electrode including a transparent conductive material or a reflective conductive material and connected to the drain electrode,
wherein the gate wire or the data wire comprises a metal film including a conductive material disposed on the insulating substrate or the gate insulating film and an opaque metal oxide film including an oxide of a conductive material disposed on the metal film,
wherein the opaque metal oxide film of the gate wire and the data wire block light, and a side of the metal film is uncovered by the opaque metal oxide film.
2. The thin film transistor array panel of claim 1 , wherein the metal film comprises one of Cr, Mo, Mo alloy, Al and Al alloy.
3. The thin film transistor array panel of claim 1 , wherein the opaque metal oxide film comprises one of oxides of Cr, Mo, Mo alloy, Al and Al alloy.
4. The thin film transistor array panel of claim 1 , wherein the conductive material included in the metal film and the conductive material included in the opaque metal oxide film are substantially the same.
5. The thin film transistor array panel of claim 1 , wherein the gate wire further includes a gate pad connected to the gate line, and the data wire further includes a data pad connected to the data line, and the thin film transistor array panel further comprises:
a subsidiary gate pad including substantially the same layer as the pixel electrode and connected to the gate pad; and
a subsidiary data pad including substantially the same layer as the pixel electrode connected to the data pads.
6. The thin film transistor array panel of claim 1 , wherein the passivation film comprises SiOC, SiOF, SiNx or an organic insulating material.
7. The thin film transistor array panel of claim 1 , wherein the semiconductor layer has substantially the same planar shape as the data wire excluding a channel portion between the source electrode and the drain electrode.
8. The thin film transistor array panel of claim 1 , wherein the pixel electrode is located on the passivation layer, and the pixel electrode and the drain electrode are connected to each other via a first contact hole provided in the passivation layer.
9. The thin film transistor array panel of claim 1 , wherein the opaque metal oxide film is formed on an entire top substantially horizontal surface of at least one of the data wire and the gate wire.
10. The thin film transistor array panel of claim 1 , further comprising a plurality of color filters facing the pixel electrodes, wherein the plurality of color filters block light.
11. The thin film transistor array panel of claim 10 , wherein portions of adjacent color filters of the plurality of color filters overlap with each other.
12. The thin film transistor array panel of claim 1 , wherein the gate wire and the data wire transmits signals and block light leakage between pixel areas.
13. The thin film transistor array panel of claim 8 , wherein the drain electrode comprises the metal film and the opaque metal oxide film, and the pixel electrode is connected to the metal film of the drain electrode.
14. The thin film transistor array panel of claim 1 , wherein the side of the metal film includes opposing sidewalls defining the metal film and the sidewalls are uncovered by the opaque metal oxide film.