Digital electronic circuit with low power consumption
View Patent ↗The digital electronic circuit ( 1 ) includes a logic cell ( 2 ) for processing data ( 82 ) , a flip-flop ( 3 ) for storing data ( 83 ) processed in the logic cell ( 2 ), a power supply ( 4 ), and a clock ( 5 ) for triggering the flip-flop ( 3 ) . The logic cell ( 2 ) is disconnected from the power supply ( 4 ) when the clock ( 5 ) is not active, as it is not needed for memorizing of the flip-flop states, and connected with the power supply ( 4 ) when the clock ( 5 ) is enabled. For switching the power supply, a switch ( 7 ) switched by the clock enable ( 6 ) is arranged between the logic cell ( 2 ) and the power supply ( 4 ). Such a simple additional switch ( 7 ) occupies only a relatively small area on the chip, but permits a drastic reduction by about 90% of the leakage currents. The circuit ( 1 ) is especially design and may be used for instance in mobile telecommunication devices.
1. A digital electronic circuit comprising:
a logic element for processing data,
a memory element for storing data processed in said logic element,
power-supply means for supplying said logic element and said memory element with electric power,
clocking means for generating a clock signal by which said memory element is triggered,
enabling means for enabling and disabling the triggering of said memory element, and
a single switching means for clearing and completing the connection between said logic element and said power-supply means, said switching means being switched by said enabling means.
2. The digital electronic circuit according to claim 1 , wherein said switching means comprise a transistor.
3. The digital electronic circuit according to claim 2 , wherein said transistor is a p-channel MOS transistor and/or an n-channel MOS transistor.
4. The digital electronic circuit according to any of the preceding claims, wherein said memory element comprises a flip-flop.
5. The digital electronic circuit according to claim 1 , 2 or 3 , wherein the circuit is manufactured in CMOS technology.
6. The digital electronic circuit according to claim 1 , 2 or 3 , wherein the circuit comprises a plurality of logic elements and a switching means is allocated to each logic element.
7. The digital electronic circuit according to claim 1 , 2 or 3 , wherein the circuit comprises a plurality of logic elements and a switching means is allocated to two or more logic elements.
8. A mobile telecommunication device comprising the digital electronic circuit according to claim 1 , 2 or 3 .
9. A method for reducing the power consumption of a digital electronic circuit, the circuit comprising:
a logic element for processing data,
a memory element for storing data processed in said logic element,
power-supply means for supplying said logic element and said memory element with electric power, and
clocking means for generating a clock signal by which said memory element is triggered,
comprising the steps of:
clearing the connection between said logic element and said power-supply means by a single switching means when the triggering of said memory element is disabled, and
completing the connection between said logic element and said power-supply means by a single switching means when the triggering of said memory element is enabled.
10. The method according to claim 9 , wherein the connection is cleared shortly after the triggering of said memory element is disabled and the connection is completed shortly before the triggering of said memory element is enabled.
11. Use of the method according to claim 9 or 10 in a mobile telecommunication device.