Nonvolatile semiconductor storage device
View Patent ↗The disclosed flash memory is provided with a majority logic circuit 3 and shift registers 6 1 to 6 3 . Three out of the banks 2 a to 2 c of the memory respectively include management information areas KAs to store binary management information comprising power supply trimming data and bitline restoration data. During initialization of the flash memory, the majority logic circuit 3 performs error correction on management information bits retrieved from the management information areas KAs and outputs that information to a trimming/restoration data buffer 11 , thus providing highly reliable management information very quickly. The shift registers 6 1 to 6 3 delay a control signal that is output from a control circuit 12 by a certain period of time before outputting the control signal to sense amplifiers 4 2 to 4 4 . This delay makes it possible to make the operating currents of the banks 2 a to 2 d start to flow at different times and to suppress a peak current flowing in the flash memory.
1. A nonvolatile semiconductor storage device which comprises a plurality of memory banks, each including a memory array in which memory cells are arranged in an array, and which is able to control parallel access to said plurality of memory banks,
wherein management information areas to store management information are provided respectively in three or more odd-numbered memory banks of said plurality of memory banks, identical management information to be read at initialization is stored in said management information areas, said nonvolatile semiconductor storage device includes a majority logic circuit which makes a majority logic decision of corresponding management information bits which have been read from said management information areas and fixes said management information, and parallel reads of said management information bits from said odd-numbered memory banks are preformed.
2. The nonvolatile semiconductor storage device according to claim 1 , wherein the management information that is stored in said management information areas comprises power supply trimming data and bitline restoration data.
3. The nonvolatile semiconductor storage device according to claim 1 , further comprising
delay circuits which delay by a certain period of time a control signal output from a control circuit for simultaneous access to said plurality of memory banks, and output a time-delayed control signal to sense amplifiers respectively connected to said memory banks.
4. The nonvolatile semiconductor storage device according to claim 3 , wherein, by the control signal that is delayed by said delay circuits, precharging bitlines of said memory banks when reading starts, delayed by a certain period of time after the start of precharging the preceding memory bank bitline.
5. The nonvolatile semiconductor storage device according to claim 3 , wherein the management information that is stored in said management information areas comprises power supply trimming data and bitline restoration data.
6. The nonvolatile semiconductor storage device according to claim 5 , wherein, by the control signal that is delayed by said delay circuits, precharging bitlines of said memory banks when reading starts, delayed by a certain period of time after the start of precharging the preceding memory bank bitline.
7. The nonvolatile semiconductor storage device according to claim 1 , wherein the memory cells arranged in said plurality of memory banks are multilevel memory cells which store data comprising two bits or more with a plurality of certain levels of threshold voltages being set.