IP Library Granted Patent US 7,567,132
Granted Patent B2
US 7,567,132 · App. 10/503,661 · Granted Jul 28, 2009

Synthesizer

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Quick Facts
Patent No.
US 7,567,132
App. No.
10/503,661
Granted
Jul 28, 2009
Kind
B2
Abstract

A synthesizer comprises a detector for detecting a parameter difference, a voltage controlled oscillator, at least one capacitor having one end connected to a node between the detector and the voltage controlled oscillator and means connected to an other end of the at least one capacitor for providing an electrical response in dependence on the detected parameter difference.

Claims (65)

1. A synthesizer comprising:

at least one detector for detecting a parameter difference;

a voltage controlled oscillator;

at least one first capacitor having one end connected to a node between said at least one detector and said voltage controlled oscillator;

at least one second capacitor having one end connected to a node between said at least one detector and said voltage controlled oscillator and another end connected to ground;

means connected to another end of said at least one first capacitor for providing an electrical response in dependence on the detected parameter difference,

wherein said response means comprises a digital to analogue converter.

2. A synthesizer comprising:

at least one detector for detecting a parameter difference;

a voltage controlled oscillator;

at least one first capacitor having one end connected to a node between said at least one detector and said voltage controlled oscillator;

at least one second capacitor having one end connected to a node between said at least one detector and said voltage controlled oscillator and another end connected to ground;

means connected to another end of said at least one first capacitor for providing an electrical response in dependence on the detected parameter difference,

wherein said response means comprises compensation means, and wherein said compensation means comprises a look up table.

3. A synthesizer comprising:

at least one detector for detecting a parameter difference;

a voltage controlled oscillator;

at least one first capacitor having one end connected to a node between said at least one detector and said voltage controlled oscillator;

at least one second capacitor having one end connected to a node between said at least one detector and said voltage controlled oscillator and another end connected to ground;

means connected to another end of said at least one first capacitor for providing an electrical response in dependence on the detected parameter difference,

wherein said response means comprises feedback compensation means and a digital to analogue converter, and wherein said compensation means is arranged to control said digital to analogue converter.

4. A synthesizer comprising:

at least one detector for detecting a parameter difference;

a voltage controlled oscillator;

at least one first capacitor having one end connected to a node between said at least one detector and said voltage controlled oscillator;

at least one second capacitor having one end connected to a node between said at least one detector and said voltage controlled oscillator and another end connected to ground;

means connected to another end of said at least one first capacitor for providing an electrical response in dependence on the detected parameter difference,

wherein said response means has an input from a node between said at least one first capacitor and said voltage controlled oscillator.

5. A synthesizer comprising:

at least one detector for detecting a parameter difference;

a voltage controlled oscillator;

at least one first capacitor having one end connected to a node between said at least one detector and said voltage controlled oscillator;

at least one second capacitor having one end connected to a node between said at least one detector and said voltage controlled oscillator and another end connected to ground;

means connected to another end of said at least one first capacitor for providing an electrical response in dependence on the detected parameter difference,

wherein said response means has an input connected to an analogue to digital converter.

6. The synthesizer of claim 1 , embodied at least partially in an integrated circuit.

7. The synthesizer of claim 1 , where said at least one detector comprises a phase detector.

8. The synthesizer of claim 1 , where said at least one detector comprises a frequency detector.

9. The synthesizer of claim 1 , where a voltage that is offset from ground is applied at the another end of said at least one first capacitor, said voltage having a value that forces an out put frequency of the voltage controlled oscillator to be close to a target output frequency.

10. The synthesizer of claim 1 , embodied as part of an apparatus configured for cellular communication.

11. The synthesizer of claim 1 , further comprising at least one additional capacitor in parallel with said at least one first capacitor.

12. The synthesizer of claim 2 , embodied at least partially in an integrated circuit.

13. The synthesizer of claim 2 , where said at least one detector comprises a phase detector.

14. The synthesizer of claim 2 , where said at least one detector comprises a frequency detector.

15. The synthesizer of claim 2 , where a voltage that is offset from ground is applied at the another end of said at least one first capacitor, said voltage having a value that forces an output, frequency of the voltage controlled oscillator to be close to a target output frequency.

16. The synthesizer of claim 2 , embodied as part of an apparatus configured for cellular communication.

17. The synthesizer of claim 2 , further comprising at least one additional capacitor in parallel with said at least one first capacitor.

18. The synthesizer of claim 3 , embodied at least partially in an integrated circuit.

19. The synthesizer of claim 3 , where said at least one detector comprises a phase detector.

20. The synthesizer of claim 3 , where said at least one detector comprises a frequency detector.

21. The synthesizer of claim 3 , where a voltage that is offset from ground is applied at the another end of said at least one first capacitor, said voltage having a value that forces an output frequency of the voltage controlled oscillator to be close to a target output frequency.

22. The synthesizer of claim 3 , embodied as part of an apparatus configured for cellular communication.

23. The synthesizer of claim 3 , further comprising at least one additional capacitor in parallel with said at least one first capacitor.

24. The synthesizer of claim 4 , embodied at least partially in an integrated circuit.

25. The synthesizer of claim 4 , where said at least one detector comprises a phase detector.

26. The synthesizer of claim 4 , where said at least one detector comprises a frequency detector.

27. The synthesizer of claim 4 , where a voltage that is offset from ground is applied at the another end of said at least one first capacitor, said voltage haying a value that forces an output frequency of the voltage controlled oscillator to be close to a target output frequency.

28. The synthesizer of claim 4 , embodied as part of an apparatus configured for cellular communication.

29. The synthesizer of claim 4 , further comprising at least one additional capacitor in parallel with said at least one first capacitor.

30. The synthesizer of claim 5 , embodied at least partially in an integrated circuit.

31. The synthesizer of claim 5 , where said at least one detector comprises a phase detector.

32. The synthesizer of claim 5 , where said at least one detector comprises a frequency Detector.

33. The synthesizer of claim 5 , where a voltage that is offset from ground is applied at the another end of said at least one first capacitor, said voltage having a value that forces an output frequency of the voltage controlled oscillator to be close to a target output frequency.

34. The synthesizer of claim 5 , embodied as part of an apparatus configured for cellular communication.

35. The synthesizer of claim 5 , further comprising at least one additional capacitor in parallel with said at least one first capacitor.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: NOKIA CORPORATION
To: NOKIA TECHNOLOGIES OY
Reel/Frame 035597/0887 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2004
From: THOMPSON, IAN V.
To: NOKIA CORPORATION
Reel/Frame 016724/0571 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2004
From: THOMPSON, IAN V.
To: NOKIA CORPORATION
Reel/Frame 016158/0145 →