IP Library Patent Application 10504559
Patent Application
App. No. 10/504,559

Electronic circuits

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Quick Facts
Patent No.
US None
App. No.
10/504,559
Abstract

A method of synchronizing a circuit comprising the steps of synchronising the circuit globally using a high-frequency clock signal, further synchronising at multiple lower frequencies by cooperative short-range state machines clocked by the high-frequency clock, and synchronising the state machines to each other by exchanging rollover signals between them.

Claims (8)

1 . A method of synchronizing a circuit comprising the steps of synchronising the circuit globally using a high-frequency clock signal, further synchronising at multiple lower frequencies by cooperative short-range state machines clocked by the high-frequency clock, amid synchronising the state machines to each other by exchanging rollover signals between them.

2 . A method according to claim 1 , comprising the further steps of resynchronising of low-speed, high propagation delay signals from Off-chip to create globally simultanous signals using latency and the fact of high-frequency synchronicity coupled to the cooperative state-machines.

3 . A method according to claim 1 or claim 2 , comprising the further step of phase locking between rotary structure where logical gating produces other than 3f (square-wave-harmonic-series) locking.

4 . A method according to claim 3 , wherein logical gating produces 2f locking.

5 . An electronic circuit synchronized according to the method as claimed in any of the preceding claims

6 . A circuit according to claim 3 , whereing the circuit is a scan circuit having SRAM-type randon access read/write method.

7 . A circuit according to claim 4 , further including gated latches.

8 . An energy conserving LC clocking system having progressive simultaneous frequency and supply voltage reduction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2007
From: MULTIGIG LIMITED
To: MULTIGIG INC.
Reel/Frame 018961/0533 →