Transferring data between differently clocked busses
View Patent ↗A method of asynchronously transferring data from a low speed bus to a high speed bus, comprises latching data at a first predetermined instant in a cycle of the clock frequency of the high speed bus, latching data at a second predetermined instant in the same cycle of the clock frequency of the high speed bus, a time period between the second and first predetermined instants being less than the period of the data, and either, if the values of the latched data at the first and second predetermined instants are equal, the latched data is transferred at a third predetermined instant onto the high speed bus, or, if the values sampled at the first and second predetermined instants are different, at the third predetermined instant, transferring the value of the currently present data is transferred onto the high speed bus.
1. A method of transferring data from a first device having a first clock frequency to a second device having a second clock frequency higher than the first clock frequency, comprising latching data at a first predetermined instant in a cycle of the second clock frequency, latching data at a second predetermined instant in the cycle of the second clock frequency, a time period between the second and first predetermined instants being less than the period of the first clock frequency, and if the values of the latched data at the first and second predetermined instants are equal, transferring the latched data at a third predetermined instant onto a bus to which the second device is coupled or if the values sampled at the first and second predetermined instants are different, at the third predetermined instant, transferring currently present data onto the bus.
2. A method as claimed in claim 1 , characterised in that the time differences between the first and second predetermined instances and between the second and third predetermined instants are substantially equal.
3. A method as claimed in claim 2 , characterised in that each of the time differences corresponds substantially to half a cycle of the clock frequency.