IP Library Granted Patent US 7,311,242
Granted Patent B2
US 7,311,242 · App. 10/507,332 · Granted Dec 25, 2007

Design of an insulated cavity

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Quick Facts
Patent No.
US 7,311,242
App. No.
10/507,332
Granted
Dec 25, 2007
Kind
B2
Abstract

The invention relates to a method for connecting a connecting surface of a first silicon wafer [WA 1 ] with a connecting surface of a second silicon wafer [WA 2 ] so as to form an insulated cavity after assembly, at least one of the two silicon wafers [WA] including at least one functional area [DA] intended to be within the cavity. The method according to the invention includes a step [PLTS] of depositing alloy soldering bumps [PLTC] on the connecting surface of the first silicon wafer [WA 1 ], said bumps [PLTC] being separated from one another by an even distance which is sufficiently small to cause joinings during the assembly of the two silicon wafers. Said step [PLTS] of depositing the soldering bumps [PLTE] is carried out during the step of depositing the soldering bumps [PLTE] intended for the electrical contacts. The method includes a reflux soldering step [RFX] for assembling the two silicon wafers by melting of the alloy soldering bumps. Application: Protection of semiconductor elements sensitive to the external conditions.

Claims (8)

1. A method for connecting a connecting surface of a first silicon wafer with a connecting surface of a second silicon wafer so as to form an insulated cavity after assembly, at least one of the two silicon wafers including at least one functional area intended to be within the cavity, said method being characterized in that it includes the steps of:

depositing a first group of alloy soldering bumps on the connecting surface of the first silicon wafer, said first group of alloy soldering bumps being separated from one another by an even distance which is sufficiently small to cause joinings during the assembly of the two silicon wafers, the said deposition of the soldering bumps being carried out during the step of depositing the soldering bumps intended for the electrical contacts,

depositing a second group of alloy soldering bumps on the connecting surface of the first silicon wafer, said second group of alloy soldering bumps being separated from one another by a distance which is sufficiently large to prevent joinings during the assembly of the two silicon wafers, and

reflux soldering in order to connect the two silicon wafers by melting of the alloy soldering bumps.

2. A method as claimed in claim 1 , also including a step of applying a resin to the contour of the cavity.

3. A method as claimed in claim 1 , for which the two silicon wafers include functional etchings.

4. A method as claimed in claim 1 , characterized in that it includes a step of filling the cavity with an inert gas.

5. A method as claimed in claim 1 , characterized in that it is implemented within an enclosure filled with an inert atmosphere.

Assignments (4)
CHANGE OF NAME Recorded Dec 12, 2017
From: IPDIA
To: MURATA INTEGRATED PASSIVE SOLUTIONS
Reel/Frame 044744/0247 →
OWNERSHIP TRANSFER Recorded Jul 16, 2010
From: NXP B.V.
To: IPDIA
Reel/Frame 024686/0839 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2007
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 019719/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2004
From: SIX, JEAN-CLAUDE
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 016147/0514 →