Granted Patent B2

US 7,075,465 · App. 10/509,828 · Granted Jul 11, 2006

Abstract

Claims (67)

1. A comparator offset calibration method for A/D converters, comprising the steps of:

providing, for each comparator in a comparator array, a common reference signal to both comparator input terminals;

forcing each comparator in said array into the same predetermined logical output state; and

adjusting, for each comparator in said array, the comparator trip-point until the logical output state is inverted; and,

adjusting each comparator trip-point by a monotonically varying signal.

2. A comparator offset calibration method for A/D converters, comprising the steps of:

providing, for each comparator in a comparator array, a common reference signal to both comparator input terminals;

forcing each comparator in said array into the same predetermined logical output state; and

adjusting, for each comparator in said array, the comparator trip-point until the logical output state is inverted; and,

simultaneously adjusting all comparators in said array by a common ramp signal.

3. A comparator offset calibration method for A/D converters, comprising the steps of:

providing, for each comparator in a comparator array, a common reference signal to both comparator input terminals;

forcing each comparator in said array into the same predetermined logical output state; and

adjusting, for each comparator in said array, the comparator trip-point until the logical output state is inverted; and,

D/A converting, for each comparator in said array, a digital ramp signal into an analog trip-point adjustment signal.

4. The method of claim 3 , further comprising the step of storing, for each comparator in said array, an offset calibration coefficient representing the digital ramp signal value that inverts its logical output state.

5. The method of claim 4 , further comprising the step of storing, for each comparator in said array, said offset calibration value externally at A/D converter power-down for later retrieval at A/D converter startup.

6. The method of claim 3 , further comprising the step of storing, for each comparator in said array, an offset calibration coefficient representing the average of an increasing digital ramp signal value that inverts its logical output state and a decreasing digital ramp signal value that inverts its logical output state.

7. The method of claim 3 , further comprising the steps of:

repeating, for each comparator in said array, said adjustment step; and

storing, for each comparator in said array, an offset calibration coefficient representing the average of several digital ramp signal values that invert its logical output state.

8. A comparator offset calibration system for A/D converters, comprising:

means for providing, for each comparator in a comparator array, a common reference signal to both comparator input terminals;

means for forcing each comparator in said array into the same predetermined logical output state;

means for adjusting, for each comparator in said array, the comparator trip-point until the logical output state is inverted; and.

means for adjusting each comparator trip-point by a monotonically varying signal.

9. A comparator offset calibration system for A/D converters, comprising:

means for providing, for each comparator in a comparator array, a common reference signal to both comparator input terminals;

means for forcing each comparator in said array into the same predetermined logical output state:

means for adjusting, for each comparator in said array, the comparator trip-point until the logical output state is inverted; and,

means for simultaneously adjusting all comparators in said array by a common ramp signal.

10. A comparator offset calibration system for A/D converters, comprising:

means for providing, for each comparator in a comparator array, a common reference signal to both comparator input terminals;

means for forcing each comparator in said array into the same predetermined logical output state;

means for adjusting, for each comparator in said array, the comparator trip-point until the logical output state is inverted; and,

means for D/A converting, for each comparator in said array, a digital ramp signal into an analog trip-point adjustment signal.

11. The system of claim 10 , further comprising registers for storing, for each comparator in said array, an offset calibration coefficient representing the digital ramp signal value that inverts its logical output state.

12. The system of claim 11 , further comprising means for storing, for each comparator in said array, said offset calibration value externally at A/D converter power-down for later retrieval at A/D converter startup.

13. The system of claim 10 , further comprising registers for storing, for each comparator in said array, an offset calibration coefficient representing the average of an increasing digital ramp signal value that inverts its logical output state and a decreasing digital ramp signal value that inverts its logical output state.

14. The system of claim 10 , further comprising:

means for repeating, for each comparator in said array, said adjustment step; and

registers for storing, for each comparator in said array, an offset calibration coefficient representing the average of several digital ramp signal values that invert its logical output state.

15. An A/D converter including at least one comparator array for flash A/D conversion of an analog signal, comprising:

means for providing, for each comparator in said array, a common reference signal to both comparator input terminals;

means for forcing each comparator in said array into the same predetermined logical output state;

means for adjusting, for each comparator in said array, the comparator trip-point until the logical output state is inverted; and,

means for adjusting each comparator trip-point by a monotonically varying signal.

16. An A/D converter including at least one comparator array for flash A/D conversion of an analog signal, comprising:

means for providing, for each comparator in said array, a common reference signal to both comparator input terminals;

means for forcing each comparator in said array into the same predetermined logical output state:

means for adjusting, for each comparator in said array, the comparator trip-point until the logical output state is inverted; and,

means for simultaneously adjusting all comparators in said array by a common ramp signal.

17. An A/D converter including at least one comparator array for flash A/D conversion of an analog signal, comprising:

means for providing, for each comparator in said array, a common reference signal to both comparator input terminals;

means for forcing each comparator in said array into the same predetermined logical output state;

means for adjusting, for each comparator in said array, the comparator trip-point until the logical output state is inverted; and,

means for D/A converting, for each comparator in said array, a digital ramp signal into an analog trip-point adjustment signal.

18. The converter of claim 17 , further comprising registers for storing, for each comparator in said array, an offset calibration coefficient representing the digital ramp signal value that inverts its logical output state.

19. The converter of claim 18 , further comprising means for storing, for each comparator in said array, said offset calibration value externally at A/D converter power-down for later retrieval at A/D converter startup.

20. The converter of claim 17 , further comprising registers for storing, for each comparator in said array, an offset calibration coefficient representing the average of an increasing digital ramp signal value that inverts its logical output state and a decreasing digital ramp signal value that inverts its logical output state.

21. The converter of claim 17 , further comprising means for repeating, for each comparator in said array, said adjustment step; and

registers for storing, for each comparator in said array, an offset calibration coefficient representing the average of several digital ramp signal values that invert its logical output state.

22. An A/D converter including at least one comparator array for flash A/D conversion of an analog signal, comprising:

means for providing, for each comparator in said array, a common reference signal to both comparator input terminals:

means for forcing each comparator in said array into the same predetermined logical output state; and,

means for adjusting, for each comparator in said array, the comparator trip-point until the logical output state is inverted;

wherein the comparators in said array comprise regenerative latches.

Assignments (8)