Processing method and apparatus for implementing systolic arrays
The present invention relates to a processing method and apparatus for implementing a systolic-array-like structure. Input data are stored in a depth-configurable register means (DCF) in a predetermined sequence, and are supplied to a processing means (FU) for processing said input data based on control signals generated from instruction data, wherein the depth of the register means (DCF) is controlled in accordance with the instruction data. Thereby, systolic arrays can be mapped onto a programmable processor, e.g. a VLIW processor, without the need for explicitly issuing operations to implement the register moves that constitute the delay lines of the array.
1. A processing apparatus for implementing a systolic-array-like structure, said apparatus comprising:
a) input means for inputting data;
b) register means for storing said input data in a predetermined sequence;
c) processing means for processing data received from said register means based on control signals generated from instruction data; and
d) register control means for controlling the depth of said register means in accordance with said instruction data; wherein said register means comprises distributed register files provided at input terminals of a plurality of functional units of said processing means; and wherein said distributed register files comprise depth-configurable FIFO register files addressable for individual registers.
2. An apparatus according to claim 1 , wherein said register control means are arranged to determine the last logical register of said FIFO register files based on control signals derived from said instruction data.
3. An apparatus according to claim 1 , further comprising at least one issue slot for storing said instruction data.
4. An apparatus according to claim 3 , wherein said register control means are arranged to use a part of the bit pattern of said instruction data stored in said at least one issue slot for controlling said depth of said register means.
5. An apparatus according to claim 1 , wherein said programmable processing apparatus is a scalable VLTW processor or a coarse-grained reconfigurable processor.
6. An apparatus according to claim 1 , wherein said distributed register files are connected to an interconnect network made up of a plurality of point-to-point connection lines.
7. An apparatus according to claim 6 , wherein said point-to-point interconnect lines have a single source.
8. An apparatus according to claim 6 , wherein said interconnect network is partially connected.
9. A processing method for implementing a systolic-array-like structure, said method comprising:
a) storing input data in a register file in predetermined sequence;
b) processing data received from said register file based on control signals generated from instruction data;
c) controlling the depth of said register file in accordance with said instruction data;
d) providing said register file with distributed register files at input terminals of a plurality of functional units; and
e) providing said distributed register files with depth-configurable FIFO register files addressable for individual registers.