Packet error signal generator
View Patent ↗A software packet error system for a High Definition Television (HDTV) receiver. A data packet error signal is transferred from a forward error correcting Reed-Solomon decoder to a transport processor. In response to a segment sync signal, the transport processor generates an error signal which appears on a programmable output pin. The software packet error signal is synchronized with the outgoing data packet signal such that each data packet is bracketed or framed by its associating packet error signal. Precession of the start of the data packets forwarded on the transport but relative to the start of the data packets appearing at the output of the decoder occurs as a result of a training packet generated for every 312 data packets. The precession is reset at the beginning of every field and is predictable across the field duration with sufficient accuracy to make the software packet error mechanism feasible.
1. A system for generating an error signal based on an error encountered while processing a received signal which includes an image representative datastream containing data packets, comprising:
a forward error detecting and correcting decoder which generates a first error signal;
a means for deriving a synchronization signal from the received signal;
a transport processor connected via a bus to the forward error detecting and correcting decoder and the means for deriving a synchronization signal so as to receive the first error signal and the synchronization signal, the transport processor generating a second error signal in response to the first error signal and the synchronization signal, wherein the second error signal begins at an earlier time than an associated data packet, and wherein the second error signal ends at a later time than the associated data packet;
a transport bus for forwarding to subsequent processing stages the data packets after having been processed by the forward error detecting and correcting decoder and wherein the data packets are forwarded as a series of discrete spaced apart frames;
wherein the second error signal is forwarded via the transport bus simultaneously with the data packets associated with the second error signal, wherein the second error signal being adapted to indicate an error in a defective data packet by having a duration that spans the frame of the defective data packet.
2. The system of claim 1 , wherein the second error signal assumes a logical low state when no error is present in a data packet.
3. The system of claim 1 , wherein the forward error detecting and correcting decoder is a Reed-Solomon decoder.
4. The system of claim 1 wherein the transport processor is implemented as a microprocessor.