Method and system for VFC memory management

1. A method for managing vertical format converter (“VFC”) line memories, the method comprising the steps of:

writing a number of first input video lines into the VFC line memories;

writing an additional video line into the VFC line memories; and

reading respective pixels of the first input video lines and the additional input video line from the VFC line memories in parallel;

wherein the step of reading respective pixels is commenced prior to completion of the step of writing the additional video line.

2. The method of claim 1 , further comprising the steps of:

concurrently with the step of reading the respective pixels, receiving an indication of a number of new input video lines to write into the VFC line memories; and

writing at least one of the new input video lines into the VFC line memories;

wherein the step of writing at least one of the new input video lines is commenced prior to completion of the step of reading respective pixels.

3. The method of claim 2 , wherein all of the steps are completed during a vertical blanking interval.

4. The method of claim 2 , wherein the additional video line includes a first pixel and a third pixel, the step of reading respective pixels is commenced after writing the first pixel of the additional video line into the VFC line memories, and the step of reading respective pixels is commenced before writing the third pixel of the additional video line into the VFC line memories.

5. The method of claim 4 , wherein the step of writing a number of first input video lines is limited to writing less than four input video lines.

6. A apparatus for managing vertical format converter (“VFC”) line memories, the apparatus comprising:

a means for writing a number of first input video lines into the VFC line memories and for writing an additional video line into the VFC line memories; and

a means for reading respective pixels of the first input video lines and the additional input video line from the VFC line memories in parallel;

wherein the means for reading respective pixels is coupled to the means for writing the additional video line, and at least one of the means for reading respective pixels and the means for writing the additional video line is configured to commence reading the respective pixels prior to a completion of the writing of the additional video line.

7. The apparatus of claim 6 , further comprising:

a means for receiving, concurrently with reading the respective pixels, an indication of a number of new input video lines to write into the VFC line memories;

wherein the means for receiving the indication is coupled to at least one of the means for reading respective pixels and the means for writing an additional video line, and the writing means includes a means for writing at least one of the new input video lines into the VFC line memories prior to a completion of the reading of the respective pixels.

8. The apparatus of claim 7 , further comprising:

a means for facilitating operations during a vertical blanking interval.

9. A digital video receiving system, comprising:

an antenna;

an input processor coupled to the antenna;

a demodulator coupled to the input processor; and

a video processor coupled to the demodulator, the video processor including vertical format converter (“VFC”) line memories and being configured to

write a number of first input video lines into the VFC line memories,

write an additional video line into the VFC line memories, and

begin reading respective pixels of the first input video lines and the additional input video line from the VFC line memories in parallel prior to a completion of the writing of the additional video line.

10. The digital video receiving system of claim 9 , wherein the video processor is further configured to

concurrently with reading the respective pixels, generate an indication of a number of new input video lines to write into the VFC line memories, and

commence writing at least one of the new input video lines into the VFC line memories prior to a completion of the reading of the respective pixels.

11. The digital video receiving system of claim 10 , wherein the video processor further includes a VFC filter coupled to the VFC line memories, and further includes a FIFO buffer coupled to the VFC filter.

12. The digital video receiving system of claim 10 , wherein the video processor is further configured to

commence reading the respective pixels after writing a first pixel of the additional video line into the VFC line memories, and

commence reading the respective pixels before writing a third pixel of the additional video line into the VFC line memories.

13. The digital video receiving system of claim 12 , wherein the video processor includes an MPEG decoder.

14. The digital video receiving system of claim 13 , further comprising:

at least one display driver coupled to the video processor; and

a display coupled to the display driver.

15. The digital video receiving system of claim 14 , wherein the display includes a high definition television plasma display unit.