Configurable processor with main controller to increase activity of at least one of a plurality of processing units having local program counters
View Patent ↗A processor comprises a main controller (CTR 11 ) and a plurality of processing units ( 1–9 ). Each processing unit ( 1–9 ) has a local controller (CTR 1 –CTR 9 ) and at least one functional unit (FU 1 –FU 9 ) controllable by the local controller (CTR 1 –CTR 9 ). The local controller (CTR 1 –CTR 9 ) of a processing unit ( 1–9 ) is coupled ( 15 ) to the main controller (CTR 11 ). The processor further comprises an instruction set, having at least one instruction for increasing the activity of at least one processing unit ( 1–9 ). The main controller (CTR 11 ) is arranged to process the at least one instruction for increasing the activity of at least one processing unit ( 1–9 ). One or more processing units ( 1–9 ) of the processor can be completely switched off, including the corresponding local controller (CTR 1 –CTR 9 ), since the instructions for switching on a processing unit ( 1–9 ) are not processed by the corresponding local controller (CTR 1 –CTR 9 ), but by the main controller (CTR 11 ) itself.
1. A processor comprising:
a main control unit including a main controller, a main program counter, and a mare instruction memory, the main instruction memory addressed by a main program counter;
a plurality of processing units, each processing unit comprising a local instruction memory addressed by a local program counter, a local controller and at least one functional unit controllable by the local controller, the local controller being coupled to the main controller; and
an instruction set stored in the main instruction memory having at least one instruction for increasing the activity of at least one processing unit; characterized in that the main controller is arranged to receive an address within the main instruction memory from the main program counter, the main controller is further arranged to process the at least one instruction.
2. A processor according to claim 1 wherein:
the instruction set further has at least one instruction for reducing the activity of at least one processing unit;
the main controller is arranged to process the at least one instruction.
3. A processor according to claim 2 wherein:
the instruction for decreasing the activity of at least one processing unit is an instruction for completely switching off the processing unit;
the instruction for increasing the activity of at least one processing unit is an instruction for completely switching on the processing unit.
4. A processor according to claim 1 wherein:
at least one processing unit further comprises a register file, the register file being accessible by the functional unit.
5. A processor according to claim 4 wherein:
the register file is a distributed register file.
6. A processor according to claim 4 wherein:
the processor further comprises a communication network for coupling the functional units of the processing units and the register files of said processing units.
7. A processor according to claim 6 wherein:
the communication network is a partially connected communication network.
8. A processor according to claim 1 wherein:
the processor is a configurable processor.