Control of contact resistance in quantum well intermixed devices

1. A method of performing quantum well intermixing in a semiconductor device structure, comprising the steps of:

a) forming a layered quantum well structure including a doped cap layer;

b) forming an etch stop layer over said cap layer;

c) forming a sacrificial layer over said etch stop layer, said etch stop layer having a substantially lower etch rate than said sacrificial layer when exposed to predetermined etch conditions;

d) carrying out a quantum well intermixing process on the device structure, which process induces significant damage to at least a portion of the sacrificial layer;

e) removing at least the sacrificial layer in at least a contact region of the device using an etch procedure selective against the etch stop layer to expose said etch stop layer in the contact region; and

f) forming a contact, over the patterned quantum well structure and directly on the surface exposed by the removal of step e), in at least said contact region.

2. The method of claim 1 in which step e) further includes the step of removing the etch stop layer using an etch procedure selective against the doped cap layer to expose said doped cap layer at least in said contact region.

3. The method of claim 2 wherein step f) includes the step of depositing a metal layer onto said doped cap layer to form said contact.

4. The method of claim 1 in which step d) comprises a heat treatment step.

5. The method of claim 1 in which step d) comprises an impurity-free vacancy disordering technique that includes the step of forming a dielectric layer on top of at least a portion of the sacrificial layer during the quantum well intermixing process.

6. The method of claim 1 wherein step f) includes the step of depositing a metal layer onto said etch stop layer to form said contact.

7. The method of claim 1 in which the sacrificial layer has one or more of similar doping levels, similar electrical properties and/or similar diffusion coefficients to the doped cap layer.

8. The method of claim 7 in which the sacrificial layer is formed from the same semiconducting material as the doped cap layer.

9. The method of claim 1 in which the layered quantum well structure comprises a substrate of a first doping level and first dopant type, a first cladding layer of a second doping level and of the first dopant type as the substrate; an optically active layer of substantially intrinsic type; a second cladding layer of a third doping level and a second dopant type; and a cap layer of a fourth doping level and second dopant type.

10. The method of claim 9 in which the first dopant type is n-type and the second dopant type is p-type.

11. The method of claim 9 in which at least one of said first cladding layer, optically active layer and second cladding layer is formed from a plurality of different sub-layers.

12. The method of claim 1 in which the doped cap layer comprises GaAs, the etch stop layer comprises GaInP and the sacrificial layer comprises GaAs.

13. The method of claim 1 in which the doped cap layer comprises GaAs, the etch stop layer comprises AlAs and the sacrificial layer comprises GaAs.

14. The method of claim 1 further including the step of forming a photonic device from said semiconductor device structure.