Address generation unit for a processor

1. A processor including:

a memory port for accessing a physical memory under control of an address;

at least one processing unit for executing instructions stored in the memory and/or operating on data stored in the memory;

at least one address generation unit (hereinafter “AGU”) for generating an address for controlling access to the memory;

the AGU being associated with at least a first set of a plurality of N registers that are used for address generation, where the set of registers enables the AGU to generate the address under control of an address generation mechanism; and

a memory unit operative to save/load k of the N registers that are used for address generation, where 2<=k<=N, triggered by one operation, where the memory unit includes a concatenator for concatenating the k registers to one memory word to be written to the memory through the memory port and a splitter for separating a word read from the memory through the memory port into the k registers.

2. A processor as claimed in claim 1 , wherein the memory unit is operative to perform the saving/loading in one write/read cycle of the memory.

3. A processor as claimed in claim 1 , wherein k=N.

4. A processor as claimed in claim 1 ,

wherein the processor includes at least one further set of a plurality of registers enabling an AGU to generate an address under control of an address generation mechanism; and

the concatenator being operative to concatenate also at least one further register of at least one of the further sets of register to the one memory word to be written to the memory through the memory port and the splitter being operative to separate a word read from the memory through the memory port into the respective k registers of the first set of registers and at least one further register of the at least one further sets of registers.

5. A processor as claimed in claim 4 ,

wherein the processor includes at least two AGUs, each for generating an address for controlling access to the memory;

each of the AGUs being associated with a respective one of the sets of a plurality of registers.

6. A processor as claimed in claim 4 , wherein the AGU is selectably connectable to at least two sets of registers, where each set of registers enables the AGU to generate a respective address under control of an address generation mechanism.

7. A processor as claimed in claim 3 , wherein the concatenator is operative to concatenate of at least two sets of registers all respective associated registers to the one memory word to be written to the memory through the memory port and the splitter being operative to separate a word read from the memory through the memory port into all the respective associated registers of at least two of the sets of registers.

8. A processor as claimed in claim 4 wherein the processor enables selection of individual sets of registers whose respective registers need to be saved or stored in one operation; and the memory unit being operative to perform the concatenation/separation to/from one memory word for the selected sets of registers.

9. A processor as claimed in claim 1 , wherein the processor is operative to operate on operands with a smallest size of one processor word and the memory word has a width of a multiple of the processor word size; and the concatenator is operative to map the registers to boundaries in the memory that correspond to the processor word to enable direct modification of a register by the processor.

10. A processor as claimed in claim 1 , wherein the processor is operative to process a plurality of M data elements in parallel, and the physical memory has a width for storing the M data elements.