Equal-amplitude signaling directional coupling bus
View Patent ↗In ultrahigh speed data transfer, a drive pulse is attenuated due to a skin effect and a dielectric loss, and a tail generated by a sub coupler extends as the drive pulse propagates on the main line. For that reason, an intersymbol interference becomes large, which causes jitters. In a memory system to which a plurality of DRAM memory modules are connected, in order to transfer data at high-speed, directional couplers are wired between a main controller and each of the modules, and the coupling lengths become longer with farther ends, thereby suppressing jitters. The directional couplers are wired between the main controller and each of the modules, and the coupling lengths are made longer with the farther ends with the results that the generated signal amounts are made constant, and jitters of the wiring and receiver delay are suppressed.
1. A bus system adapted to transfer data between a plurality of semiconductor devices, comprising:
a first wiring extending in a first direction from a first semiconductor device;
n-coupling wirings forming directional couplers extending in sequence away from said first semiconductor device in said first direction, each of said directional couplers being parallel to said first wiring; and
n semiconductor devices, different from the first semiconductor device, each respectively connected to a corresponding one of said directional couplers,
wherein each of the directional couplers has a predetermined coupling length and a predetermined wiring interval of spacing from the first wiring,
wherein the coupling lengths of the directional couplers decrease as the respective distance of the directional couplers from the first semiconductor device increases, and
wherein the wiring intervals of spacing of the directional couplers from the first wiring decrease as the respective distances of the directional couplers from the first semiconductor device increase.
2. A bus system according to claim 1 , wherein the first semiconductor device is a memory controller.
3. A bus system according to claim 1 , wherein the n semiconductor devices are DRAMS.
4. A bus system according to claim 2 , wherein the n semiconductor devices are DRAMS.