IP Library Granted Patent US 6,998,654
Granted Patent B2
US 6,998,654 · App. 10/520,155 · Granted Feb 14, 2006

Semiconductor integrated circuit device

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Quick Facts
Patent No.
US 6,998,654
App. No.
10/520,155
Granted
Feb 14, 2006
Kind
B2
Abstract

A semiconductor integrated circuit device ( 10 ) is composed of an LSI function unit ( 11 ) and a shield wiring layer ( 22 ) formed on the unit. The LSI function unit ( 11 ) includes a semiconductor substrate ( 12 ) and a first insulating film ( 13 ), and the semiconductor substrate ( 12 ) is formed with a circuit element including, for example, a MOS transistor ( 14 ). The shield wiring layer ( 22 ) is composed of a lower shield line ( 23 ), a third insulating film ( 24 ), an upper shield line ( 25 ), and a fourth insulating film ( 26 ) sequentially stacked above a second insulating film ( 17 ). The directions in which the lower and upper shield lines ( 23 ) and ( 25 ) are arranged intersect each other.

Claims (36)

1. A semiconductor integrated circuit device comprising:

an integrated circuit; and

a shield wiring layer formed above the integrated circuit and preventing a physical alteration to the integrated circuit,

wherein the shield wiring layer includes a lower shield line and an upper shield line formed above the lower shield line,

the directions in which the lower shield line and the upper shield line are arranged intersect each other,

the lower shield line comprises a plurality of lower shield lines and the upper shield line comprises a plurality of upper shield lines, and

the device further comprises a selector circuit which electrically connects at least two of the plurality of lower shield lines and/or the plurality of upper shield lines and which can change the line targeted for this connection.

2. The device of claim 1 ,

wherein the selector circuit comprises a plurality of selector circuits, and

the plurality of selector circuits are provided above the integrated circuit to have random intervals.

3. A semiconductor integrated circuit device comprising:

an integrated circuit; and

a shield wiring layer formed above the integrated circuit and preventing a physical alteration to the integrated circuit,

wherein the shield wiring layer includes a lower shield line and an upper shield line formed above the lower shield line,

the directions in which the lower shield line and the upper shield line are arranged intersect each other, and

at least one of the lower shield line and the upper shield line has a connector connected to a power source line, a ground line, or a signal line for controlling the integrated circuit.

4. The device of claim 3 ,

wherein the connector comprises a plurality of connectors and the plurality of connectors are provided above at least one of the lower shield line and the upper shield line, and

the plurality of connectors are provided above the integrated circuit to have random intervals.

5. The device of claim 4 ,

wherein at least one of the lower shield line and the upper shield line is formed with a plurality of dummy vias randomly arranged without being electrically connected to the signal line.

6. A semiconductor integrated circuit device comprising:

an integrated circuit; and

a shield line formed above the integrated circuit and preventing a physical alteration to the integrated circuit,

wherein the directions in which the shield line and an interconnection line of the integrated circuit are arranged diagonally intersect each other.

7. The device of claim 6 ,

wherein the shield line comprises a plurality of shield lines, and

the device further comprises a selector circuit which electrically connects at least two of the plurality of shield lines and which can change the line targeted for this connection.

8. The device of claim 7 ,

wherein the selector circuit comprises a plurality of selector circuits, and

the plurality of selector circuits are provided above the integrated circuit to have random intervals.

9. The device of claim 6 , wherein the shield line has a connector connected to a power source line, a ground line, or a signal line for controlling the integrated circuit.

10. The device of claim 9 ,

wherein the connector comprises a plurality of connectors and the plurality of connectors are provided above the shield line, and

the plurality of connectors are provided above the integrated circuit to have random intervals.

11. The device of claim 10 , wherein the shield line is formed with a plurality of dummy vias randomly arranged without being electrically connected to the signal line.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →
CHANGE OF NAME Recorded Mar 18, 2020
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 052184/0943 →