Stereo signal processing apparatus
View Patent ↗Disclosed is a stereo signal processing apparatus, in particular for a digital BTSC television decoder, comprising a sub-channel signal processing section which comprises an input for inputting an input sub-channel signal, a DBX expanding means and an output for outputting an output sub-channel signal. The particularity of the present invention is that said sub-channel signal processing section further comprises a phase error compensating means for correcting a phase error of said DBX expanding means so that at said output of said sub-channel signal processing section the phase of the output sub-channel signal is essentially constant or zero over a predetermined frequency range.
1. A stereo sub-channel signal processor circuit comprising: an input circuit configured to receive a multichannel digital television signal including a main channel and a sub-channel of the digital television signal; a DBX expander circuit configured to expand and output an expanded sub-channel signal of the digital television signal to provide an audio signal; and a phase error compensator circuit connected between the input circuit and the DBX expander circuit and configured to process the received sub-channel of the digital television signal to compensate for a phase error in the DBX expander circuit and to set the phase of the expanded sub channel output signal to a phase that is about constant over a predetermined frequency range, wherein the phase error compensator circuit is configured to process the received sub-channel of the digital television signal to compensate for a phase error in the DBX expander circuit by variably modifying the phase of the received sub-channel signal, based upon an amplitude of the received sub-channel signal, to generate and output a modified sub-channel signal to the DBX expander circuit to set the phase of the expanded sub-channel output signal; and wherein the phase error compensator circuit includes a variable phase delay filter that processes the received sub-channel of the digital television signal to compensate for phase error up to about one-fourth of a scanning frequency for the digital television signal, and coupled between the input circuit and the variable phase delay filter, a fixed phase shift filter to format a phase error portion of the received sub-channel of the digital television signal to a phase response of the variable phase delay filter, to facilitate compensation by the variable phase delay filter at frequencies of up to about half of a scanning frequency for the digital television signal.
2. The processor circuit according to claim 1 , characterized in that said phase error compensating circuit includes a linear level depending phase error correction means having a variable phase delay filter with an extended mixer functionality.