Digital filter for reducting blocking artifacts in images
View Patent ↗The present invention relates to a digital data filtering circuit. This digital data filtering circuit is able to implement the calculation steps of a discrete transform of a set of 8 original data (w), and calculating an inverse discrete transform of the set of transformed data thus obtained. For this purpose, it comprises a first filtering module (FILo 1 ) intended to filter the odd transformed data or the 3 odd transformed data items having the highest frequencies in the set of transformed data, and a second filtering module (FILo 2 ) connected to the first filtering module and intended to filter the 2 odd transformed data having the highest frequencies in the set of transformed data.
1. A digital data filtering circuit to correct blocking artifacts in a frequency domain within a block-based video processing device, the digital data filtering circuit comprising:
means for performing a discrete linear transform to transform a set of input luminance values, from two adjacent video segments, into a corresponding set of transformed values in the frequency domain, wherein the transformed values in the frequency domain comprise a plurality of even transformed data values and a plurality of odd transformed data values;
means for performing an inverse discrete linear transform to transform the transformed values from the frequency domain to a corresponding set of filtered values for use on a display device coupled to the video processing device; and
a control circuit coupled to the means for performing the discrete linear transform and the inverse discrete linear transform, wherein the control circuit is configured to selectively activate at least one of a plurality of filtering modules, wherein the plurality of filtering modules comprises at least one odd filtering module to filter at least one of the odd transformed data values and at least one even filtering module to filter at least one of the even transformed data values.
2. The digital data filtering circuit of claim 1 , wherein the control circuit is further configured to selectively activate the at least one of the plurality of filtering modules based on a predicted maximum frequency (kwpred) and a quantization step (Q).
3. The digital data filtering circuit of claim 1 , wherein the means for performing the discrete linear transform and the inverse discrete linear transform comprise:
a first odd filtering module (FILo 1 ) of the plurality of filtering modules, wherein the first odd filtering module is configured to filter three of the odd transformed data values, wherein the three odd transformed data values filtered by the first odd filtering module comprises:
a first odd transformed data value having a highest frequency out of the odd transformed data values;
a second odd transformed data value having a second highest frequency out of the odd transformed data values; and
a third odd transformed data value having a third highest frequency out of the odd transformed data values; and
a second odd filtering module (FILo 2 ) of the plurality of filtering modules, the second odd filtering module coupled to the first filtering odd module, wherein the second odd filtering module is configured to filter the first and second odd transformed data values having the highest and second highest frequencies, respectively.
4. The digital data filtering circuit of claim 3 , wherein the means for performing the discrete linear transform and the inverse discrete linear transform further comprise:
discrete transform means coupled to the control circuit, the discrete transform means to transform a first half of the set of input luminance values into a first half of the transformed values in the frequency domain, and to transform a second half of the set of input luminance values into a second half of the transformed values in the frequency domain; and
an even filtering module (FILe) coupled to the control circuit, wherein the even filtering module is configured to filter at least one of the even transformed data values, wherein the at least one even transformed data value filtered by the even filtering module comprises a first even transformed data value having a highest frequency out of the even transformed data values.
5. The digital data filtering circuit of claim 4 , wherein the even filtering module is further configured to filter the first even transformed data value and a second even transformed data value, wherein the second even transformed data value comprises a second even transformed data value having a second highest frequency out of the even transformed data values.
6. The digital data filtering circuit of claim 4 , wherein the discrete transform means is further configured to transform the first and second halves of the set of input luminance values into the first and second halves of the transformed values in the frequency domain, respectively, in succession at a double frequency.
7. The digital data filtering circuit of claim 4 , wherein the first half of the set of input luminance values comprises data of even parity from one of the two adjacent video segments, and the second half of the set of input luminance values comprises data of even parity from the other of the two adjacent video segments.
8. The digital data filtering circuit of claim 4 , wherein the first half of the set of input luminance values comprises data of odd parity from one of the two adjacent video segments, and the second half of the set of input luminance values comprises data of odd parity from the other of the two adjacent video segments.
9. The digital data filtering circuit of claim 4 , wherein the first half of the set of input luminance values comprises highest rank data one of the two adjacent video segments, and the second half of the set of input luminance values comprises lowest rank data from the other of the two adjacent video segments.
10. A video decoder comprising the digital data filtering circuit of claim 1 , wherein the video decoder is configured to supply filter digital images and supply decoded digital images to the display device.
11. A portable apparatus comprising the digital data filtering circuit of claim 1 and the display device, wherein the portable apparatus is configured to display filtered digital images on the display device.
12. A television receiver comprising the digital data filtering circuit of claim 1 , wherein the television receiver is configured to filter digital images received by the television receiver and to display filtered digital images on a screen coupled to the television receiver.